HDL设计数字UART(中英文翻译).doc

毕业设计(论文)英文翻译 题 目 : 基于FPGA的串口控制器设计院、系(部): 专业及班级: 姓 名: 学 号: 指 导 教 师 : 日 期 : 译文基于FPGA的串口控制器设计简介使用硬件描述语言 (HDL) 设计和开发验证FPGA的成为当前的主流因素。使用行为级描述不只增加了产品的设计效率，也在设计中有独特的验证方式。目前最流行的HDL语言为Verilog 和 VHDL。 这篇文章将会举例说明用 Verilog语言 的设计和验证数字异步串行收发器UART。UART介绍通用异步串行收发器UART中有二个独立的VHDL模块。 一个模块实现发射功能, 当另一个实现接收功能， 发射和接收功能模块在顶端设计时组合到一起使用,接收和发射的组合是通信通道所必需的。 数据写入发射器，从接收器读出，所有的数据是以二进制8字节的信号通过CPU接口。在顶端设计时，地址有发射器映射，而且接收器通道能容易地建立从儿进入接口， 两者工用一个称为mclkx 16主控时钟，在每个模块中 mclkx 16 被分成独立的波特率时钟。UART的功能概况 UART的基本功能概况见下表. 在左边显示传输保持记录，移位记录，传输控制时钟，全部集中在发射机的txmit端。在右边的是显示接收移位寄存器, 接收记录和控制逻辑时钟，所有都包含在接收模块的rxcver端，这两个模组都单独的投入与产出,大部分的控制线,只有双向数据总线, 主时钟和复位线共享的模块。顶层UART系统的I/O功能描述UART的标准数据格式图3显示了UART的串行数据格式， 串行数据包含在帧8个数据字节,以及编码信息比特，在连续传输线路高通， 在传输初始化时开始低一点.，接下来的低一点开始到8比特的数据信息, 低位对于后边高位有重要的作用。然后后边的8 bits数据进行奇偶校验 ,反馈8位数据的结果。UART时序图下面显示怎么将从寄存器里出来的数据写给移位寄存器，并在上升沿速率时钟时,转向tx输出。发送时间如下表，如何得到数据从rx传输到接收移位寄存器然后存储。发送器主控时钟称为mclkx16，分频成正确的等于mclkx16/16的txclk波特率。数据以平行的形式锁存模块，而转向以串行格式的tx输出波特率时钟频率。数据转到tx输出跟随串行数据格式显示在图6。发送器行为描述发送器等待新的数据来写入模块，新的数据在发送器初始化后发送。数据以并行方式传送串行数据帧的tx输出. 当没有传输序列的地方, tx输出是高通。发送器实现产生逻辑的Verilog始于模块端口的声明，这里定义的信号,是移植到从单元，没有方向指明这一点。在下一个端口定义来自端口的方向，方向指定为输入,输出或(双向) ,见表1。指明端口方向来声明内部信号， 内部信号的Verilog称为wire和reg数据类型，WIRE被数字低音的分配，REG用在分配Verilog里的always时钟，座,常常使用逻辑顺序的分配,但不是一定的，进一步解释见Verilog参考书，数据类型的内部信号如表3 。我们现在已经通过了所有必要的声明,并已作好准备,看看实际执行， 用硬件描述语言使我们描述的功能的发送器更加行为化, 而不是把重点放在它门级。在软件编程语言，职能和工作程序分成更具可读性和易处理，一个Verilog的功能及任务是作为相当于复线Verilog代码, 如果某些输入信号或某些影响产出或变数. 使用的职能和任务,通常发生在多行代码都是重复使用的设计, 从而使得设计易于阅读和维护肯定，一个Verilog的功能,可以有多种输入,但始终只有一个输出, 虽然Verilog任务可以兼得多投入,多产出,甚至在某些情况下, 非取长补短，下面显示了Verilog任务,即拥有所有必要的顺序语句,用来描述发送器的转移模式。我们可以看到在移位寄存器有2个标志位tag1和tag2，在描述空闲和置位模块时产生相同的作用，使用这些 Verilog 工作, 现在我们可以产生一个容易阅读的行为模型的空穴传输过程。如果txdone and txdatardy都是正确的，进入发送器负荷模式. 接下来的负载模式下,进入发送模式转变.，在上升沿的速率时钟,内容tsr转移到tx输出. 奇偶校验过程产生于tsr变化中,如下所示。重要的一点,就是tsr为零发生在传输过程， 在不同的数据传输时标志位tag 和tsr赋零。传输序列的模拟在写上升沿时数据总线容量被锁存，在下一上升沿txclk，thr的容量载入tsr，低电平开始位进入tx，发送标志位显示，thr再次等待新的数据的写入。在每个发送时钟上升沿，tsr的容量被送入tx，在数据传输过程中发生奇偶校验，周期循环时奇偶校验为高，tx产生奇偶检验结果。接收模块主控时钟mclkx16分频到合适的波也率时钟称为rxclk，它等于mclkx16/16 . 串行数据为收到的rx输入模块，要按照UART的数据格式显示为图3，收到的数据格式以并行形式读出,通过8位数据总线。接收模块行为描述在连续发送时，发送保持高，根据标准异步串行UART，接收器在等待闲置模式的rx输入要低，在rx下降沿接收进入保持模式，现在寻求一种有效的开始位等待新的数据帧的到来，当有效的开始位被检测到时，接收器回到闲置模式，在接收一个数据帧,各种校验和检查错误，当一个完整的数据帧收到接收端返回待机模式.，接收器基本运作如下所示。接收频率为mclkx16，和第一上升沿的rxclk常常发生在中心点开始位，如下图显示，对于中心点的起始位及后边的数据字节，波特率时钟是同步。接收器模块的实现为了产生一个易读易操作的接收器模块，用两中Verilog功能来描述不同的接收方式，当接收在空闲状态时，其中一个Verilog称为空闲复位，而它需要所有必要的顺序语句来描述接收机复位条件。当接收器不在复位状态，也不在空闲状态下，rx输入端的采样数据，传输到移位寄存器中，在进入的数据中产生奇偶校验位，另外一个Verilog称为数据移位，需要所有必要的顺序语句来描述上述行为。利用两个Verilog实现上述功能，现在在复位状态，空闲状态或者数据传输状态，我们可以产生行为级描述的接收器，所有上述行为是和接收时钟同步的，它们的实现如下所示。当低电平开始位到达rsr0时，一个完整的数据帧将会给接收到，在下一个接收时钟上升沿到来是又回到空闲状态，当返回空闲状态时，接收器显示数据接收准备，然后数据以并行方式读出，错误的标识更新，并返回空闲状态，在数据读出后清除，在读下降沿，rhr的容量锁存在数据总线，表8所示接收器各种错误检查。接收序列的模拟在连续传输时线路高通， 在rx输入下降沿，,内部rxcnt开始计数，和mclkx16同步，如果rx输入在mclkx16的 8个周期循环，内部空闲复位，接收时钟产生使能，和中心低开始位同步，在接受时钟上升沿，数据从RX传输到RSR，当低开始位到底rsr0时，在下一个接收时钟上升沿又被置空闲位，此时失效，在接收序列，刚好产生rxclk的11个周期，为采样一位低开始位，一位数据位，一位奇偶位，一位置高停止位。在返回空闲状态，rsr被置入rhr，内部标志位更新，接收位产生,rhr容量给读出，在读下降沿，rhr应用到数据总线。硬件描述语言仿真我们现正研究如何HDL可用于行为级设计,实现了数字UART 。在HDL进行设计的实施更容易阅读,并希望能理解, 它还规定,能够方便的描述依存度之间的各种程序,通常是发生在这样一个复杂 事件驱动系统，例如UART，我们很快将看到这种依靠各种进程来描述的能力对于实现模拟是确实必须的。Verilog语言中的模拟激励叫做测试工具，测试工具的Verilog模块,拥有各线路的HDL代码要生成仿真激励, 而在同一时间端口影射，这些产生的信号将会模拟。端口影射是完成了被异步通用步收发传输器的级层模块实例化顶端水平进入测试工具，如下所示。这使得仿真激励适用于输入的设计，同时检测输出的设计，输入激励,可以有条件地反应与输出，图19显示说明如何测试工具端口影射到UART的顶层。在测试工具的输出的传输模块又循环到接收器的输入模块，这使得发送器模块用来作为测试信号发生器接收器模块，数据可以并行的方式向发送器，同时回送到输入的接收机模块，收到的数据最终从接收器以并行格式读出，为了尽可能实现UART的自动化测试，独立书Verilog功能如下，发送写入功能需要一切必要的声明来产生一个并行的数据写序的发送器，数据写入发送器来完成写入接收功能，锁存内部测试工具供以后的分析。接收读出功能需要一切必要的声明来产生一个并行的数据写序的接收器，数据读出接收器来完成读出功能，锁存内部测试工具供以后的分析。数据比较功能需要一切必要的声明来同先前写入发送器，相应的最新接收数据和接收模块读出的数据比较，如果发生任何误差，数据比较标志一个从发送器写出的数据定义错误，相应的数据也从接收模块接收和读出，有任何误差发生时，笔记比较数据功能将立即停止模拟仿真。综合HDL作为设计方法比传统的FPGA设计输入方式如原理图方式有若干优势，它同时规定了极大的灵活性以及高性能的目标装置的综合流程，UART综合流程已针对两个灵活和高性能的可编程逻辑器件FPGA系列，如pASIC-1和pASIC。UART设计和模拟的文件进入叫做使用HDL语言编辑器的Saros Technologies的turbow软件，HDL设计合成了快速高效的正确综合工具，综合以后，设计布局使用spde可编程逻辑工具，在布局之后,UART使用有标注的Verilog布局时序模块，快速Verilog仿真为来自Simucad的SilosIII后布局仿真，所有使用过的工具中可用的工具来自于快速逻辑。 The serial controller design based on FPGAIntroductionThe use of hardware description language (HDL) is becoming a more dominant factor, when designing and verifying FPGA designs. The use of behavior level description not only increases the design productivity, but also provides unique advantages in the design verification. The most dominant HDL stoday are called Verilog and VHDL. This application note will illustrate the use of Verilog in design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).Defining the UART.The UART consists of two independent HDL modules. One module implements thetransmitter, while the other module implements the receiver. The transmitter and receivermodules can be combined at the top level of the design, for any combinations of transmitter and receiver channels required. Data can be written to the transmitter and read out from the receiver, all through a single 8 bit bi-directional CPU interface. Address mapping for the transmitter and receiver channels can easily be build intothe interface at the top level of the design. Both modules share a common master clock called mclkx16. Within each module mclkx16 are divided down to independent baud rate clocks.UART functional overview.A basic overview of the UART is shown below. At the left hand side is shown “transmit hold register”, “transmit shift register” and the transmitter “control logic” block, all contained within the transmitter module called “txmit”. At the right hand side is shown the “receive shift register”, “receive hold register” and the receiver “control logic” block, all contained within the receiver module called “rxcver”. The two modules have separate inputs and outputs for most of their control lines, only the bi-directional data bus, master clock and reset lines are shared by both modules.The UART standard data format.In figure 3 is shown the UART serial data format. Serial data are contained within frames of 8 data bits, as well as coded information bits. Between successive transmissions, the transmission line is held high. A transmission is initialized by a leading low start bit. Next to the leading low start bit comes 8 bits of data information, beginning with the LSB and afterwards represented at increasing significance order up to the MSB. Next to the 8 data bits comes the parity bit, representing the parity result of the 8 data bits. The parity bit can be encoded true based on even parity or odd parity mode. Next to the parity bit comes atrailing high stop bit indicating the end of a data frame.UART timing diagrams.Below is shown, how data written to the “transmit hold register” gets loaded into the “transmit shift register”, and at the rising edge of the baud rate clock, shifted to tx output.Below is shown, how data gets shifted from rx input to the “receive shift register”, and afterwards loaded into the “receive hold register”. Finally the receiver raises “rxrdy” flag.The Transmitter module.The master clock called mclkx16 are divided down to the proper baud rate called txclk and equals to mclkx16/16. Data written in parallel format to the module are latched internally, and shifted in serial format to the tx output at the frequency of the baud rate clock. Data shifted to the tx output follows the UART data format shown in fig. 3.Behavioral description of the transmitter.The transmitter waits for new data to be written to the module. When new data are written a transmit sequence is initialized. Data that was written in parallel to the module gets transmitted as serial data frames at the tx output. When no transmit sequence are in place, the tx output is held high.Implementation of the transmitter module.Creating logic in Verilog starts with the module port declaration. Here defines signals, that are ported to and from the module. No direction are specified at this point.Next to port definitions comes port directions. Directions are specified as input, output or inout (bidirectional), and can be referred to in table 1. Next to the specification of port directions comes declaration of internal signals. Internal signals in Verilog are declared as “wire” or “reg” data types. Signals of the “wire” type are used for continuos assignments, also called combinatorial statements. Signals of the “reg” type are used for assignments within the Verilog “always” block, often use forsequential logic assignments, but not necessarily. For further explanation see aVerilog reference book. Data types of the internal signals of the module can be referred to in table 3.We have now passed by all necessary declarations, and are now ready to look at the actual implementation. Using hardware description language allows us to describe the function of the transmitter in a more behavioral manner, rather than focus on its actual implementation at gate level In software programming language, functions and procedures breaks larger programs into more readable, manageable and certainly maintainable pieces. The Verilog language provides functions and tasks asconstructs, analogous to software functions and procedures. A Verilog function and task are used as the equivalent to multiple lines of Verilog code, where certain inputs or signals affects certain outputs or variables. The use of functions and tasks usually takes place where multiple lines of code are repeatedly used in a design, and hence makes the design easier to read and certainly maintain. A Verilog functioncan have multiple inputs, but always have only one output, while the Verilog task can have both multiple inputs, and multiple outputs and even in some cases, non of each. Below is shown the Verilog task, that hold all necessary sequential statements, to describe the transmitter in the “shift” mode.We here see the two tag bits called tag1 and tag2 concatenated to the “transmit shift register. Similar tasks were created to describe the transmitter in “idle” and “load”modes. By using these Verilog tasks, we can now create a very“ easy to read” behavioral model of the hole transmit process.If txdone and tx datardy both are true, the transmitter enter load mode. Next to the load mode, the transmitter enters shift mode. At the rising edge of the baud rate clock, the contents of tsr are shifted to the tx output. Parity generation takes place during shifting of the tsr, as shown below.Its important to note, that the tsr are zero filled during transmission. The combination of the two trailing tag bits and the zero filled tsr indicates the different states during shifting. Paritycycle is high on cycle next to last cycle, that means when tsr1 gets tag2.Txdone is high when shifting is over, this means when tx gets tag2.Based on the different states during the transmission sequence, “data bits”, “parity bit” or “stop bit” are ultiplexed to the tx output.Simulation of a transmit sequenceThe contents of the data bus are latched into thr at the rising edge of write. At the next rising edge of txclk, the contents of thr are loaded into tsr, the active low start bit is asserted to tx, and the txrdy flag indicates, that thr again is ready for new data to be written. At each rising edge of txclk, the contents of tsr is shifted totx. Parity generation takes place during shifting of data. Parity cycle is high one cycle next to last cycle, and tx gets the parity result. The internal txdone is high when shifting is over, and the active high stopbit is asserted to tx.For further details on the implementation can be referred to in the design source file available fromThe Receiver module.The master clock mclkx16 are divided down to the proper baud rate clock called rxclk, and equals to mclkx16/16. Serial data to be received at the rx input of the module, must follow the UART data format shown in fig. 3. Data received in serial format can be read out in parallel format, through the 8 bit data bus.Behavioral description of the receiver.Between successive transmissions, the transmission line is held high, according to standard UART behavior. The receiver waits in “idle” mode for the rx input to go low. At the falling edge of rx the receiver enter “hunting” mode, now searching for a valid start bit of a new data frame to be received. If a valid start bit is detected, the receiver enter “shift data” mode. If an invalid start bit is detected, the receiver returns to “idle” mode. During receive of a data frame, various parity and error checks are performed. When a complete data frame has been received the receiver returns to idle mode. The basic operation of the receiver works as shown below,The frequency of rxclk are equal to mclkx16/16, and the first rising edge of the rxclk will always occur at the center point of the start bit. Below is shown, how generation of the baud rate clock rxclk are synchronized to the center points of the start bit and the following data bits.Implementation of the receiver module.In order to create an easy to read and easy to maintain behavioral model of the receiver, two Verilog tasks are written to describe the different modes of the receiver. The Verilog task called “idle_reset” holds all necessary sequential statements to describe the receiver at reset condition, and when the receiver is in its idle mode.When the receiver is not at its reset condition, and not in its idle mode, the receiver samples data at the rx input, shifts the data to the “receive shift register”, and generates parity based on the incoming data. The Verilog task called “shift_data” holds all necessary sequential statements to describe all above actions. Using the two Verilog tasks described above, we are now able to create the behavioral level description of the receiver at its reset condition, idle mode or when shifting in data. All above actions is synchronous to the baudrate clock called rxclk, and the implementation is shown below.A complete data frame has been received, when the leading low start bit reaches rsr0, and the receiver returns to idle mode again at the next rising edge of rxclk. At return to “idle” mode the receiver raises the “receive data ready” interrupt to indicate, that the new data received now can be read out in parallel format. Error flags are updated as well upon return to “idle” mode, and cleared when data are read out of the receiver. At the falling edge of read, the contents of the rhr are latched to the data bus. In table 8 shown below are the various error checks supported by the receiver.Simulation of a receive sequence.Between successive transmissions, the transmission line is held high. At the falling edge of rx input, the internal rxcnt starts counting up, synchronous to mclkx16. If rx input stays low for 8 cycles of mclkx16, the internal status bit idle is reset, and there by enable generation of rxclk. Rxclk is now synchronized to the center point of the low start bit. At the rising edge of rxclk, data are shifted from the rx input to rsr. When the leading low start bit reach rsr0, the next rising edge of rxclk forces idle high again, and there by disable generation of rxclk. During a receive sequence, exactly 11 cycles of rxclk is generated, in order to sample a total of 1 leading low start bit, 8 data bits, 1 parity bit and 1 trailing high stop bit. At return to idle mode, the contents of rsr are loaded into rhr, the status flags are updated. The flag “rxrdy” now indicates, that the contents of rhr can be read out. At the falling edge of read, the contents of rhr are applied to the data bus.Using Hardware Description Language for Simulation.We have now studied how HDL can be used for the behavioral level design implementation of a digital UART. While HDL make the design implementation easier to read and hopefully to understand as well, it also provides the ability to easily describe dependency in between various processes that usually occur in such a complex event driven systems, as for example the UART. This ability to describe dependency in between various processes is extremely need for simulation purposes as we will see very soon. Simulation stimulus in Verilog HDL is called a “test fixture”. A test-fixture is a Verilog module that holds all lines of HDL code necessary to generate the simulation stimulus, while it at the same time port maps these signals to the design that are to be simulated. The port mapping is done by hierarchical module instantiation of the UART top level module into the test-fixture, as shown below.This allows simulation stimulus to be applied to the inputs of the design, while monitoring the outputs of the design. Input stimulus can be made conditionally to the response on the outputs ect. In fig. 19 shown below is illustrated, how the test-fixture port maps to the top level of the UART.Within the test-fixture the tx output of the transmitter module is looped back to the rx input of the receiver module. This allows the transmitter module to be used as test signal generator for the receiver module. Data can be written in parallel format to the transmitter module and looped back in serial format to the rx input of the receiver module, and data received can finally be read out in parallel format from the receivermodule. In order to automate the testing of the UART as much as possible, tree independent Verilog tasks were written as follows. The Verilog task“write_to_transmitter” holds all necessary statements required to generate a single parallel data write sequence to the transmitter module. Data that are written to the transmitter upon execution of