DS1302数据手册翻译.pdf

FEATURES Real time clock counts seconds minutes hours dateofthe month month day of the week and year with leap year compensation validupto 2100 31 x 8 RAM for scratchpad data storage Serial I O for minimum pin count 2 0 5 5Vfulloperation Uses less than 300nAat 2 0V Single byte or multiple byte burst mode data transfer for read or write of clock or RAM data 8 pin DIP or optional 8 pin SOICsfor surface mount Simple 3 wire interface TTL compatible VCC 5V Optional industrial temperature range 40 C to 85 C DS1202 compatible Recognized by Underwriters Laboratory 特性 能计算秒 分 时 日期 星期 月份和年的实时时钟 具有闰年补偿功能 有效期到2100年 31字节高速暂存 RAM 可用于数据存储 只需要最少的串行 I O 口 工作电压2 0 5 5V 2 0V 工作时电流小于300nA 单字节数据 突发模式下允许多字节数据传输 可读写时钟数据或者 RAM 内数据 8 PDIP 或者8pin soic 封装 精简的3线接口 兼容 TTL 适用温度范围 40 C to 85 C 向下兼容 DS1202 Underwriters Laboratory 可靠认证 PINDESCRIPTION X1 X2 32 768 kHz Crystal Pins GND Ground RST Reset I O Data Input Output SCLK Serial Clock VCC1 VCC2 Power Supply Pins DESCRIPTION The DS1302 Trickle Charge Timekeeping Chip contains a real time clock calendar and 31 bytes of static RAM Itcommunicates with a microprocessor via a simple serial interface The real time clock calendar provides seconds minutes hours day date month and year information The end of the month dateisautomatically adjusted for months with less that 31 days including corrections for leap year The clock operates in either the 24 hour or 12 hour format with an AM PM indicator Interfacing the DS1302 with a microprocessorissimplifiedbyusing synchronous serial communication Only three wires are required to communicate with the clock RAM 1 RST Reset 2 I O Data line and 3 SCLK Serial clock Data can be transferred to and from the clock RAM 1 byte at a time or in a burst of up to 31 bytes The DS1302isdesigned to operate on very low power and retain data and clock information on less than 1 microwatt The DS1302isthe successor to the DS1202 In addition to the basic timekeeping functionsofthe DS1202 the DS1302 has the additional features ofdualpower pins for primary and back uppower supplies programmable trickle charger for VCC1 and seven additional bytes of scratchpad memory 描述 涓流充电式 DS1302时钟芯片内部包含一个实时时钟 日历电路和一个 31字节的静态存储器 通过很少的串行接口即可以实现和微处理器的通信 时钟 日历电路能提供秒 分 时 日期 星期 月份和年等信息 具有闰年和闰月 自动调整功能 时钟数据可以用12或24小时制表示 DS1302和微处理器通信采用简化了的同步串行方式 只需要三个 GPIO 分别是 RST I O SCLK 对 clock RAM 的访问可以采用每次1字节的方 式 在突发模式下 最多每次可达到31字节 DS1302拥有极低的操作功耗 保 存数据的功耗低于1微瓦 DS1302在 DS1202的基础上增加了后备电源 VCC1可编程涓流充电 而且高速暂存存储器也多了7个字节的单元 OPERATION The main elements of the Serial Timekeeper are shown in Figure 1 shift register control logic oscillator real time clock and RAM 内部结构见图1 SIGNAL DESCRIPTIONS VCC1 VCC1 provides low power operation in single supply and battery operated systems aswellas low power battery backup In systems using the trickle charger the rechargeable energy sourceisconnected to this pin VCC2 Vcc2isthe primary power supply pin in a dual supply configuration VCC1isconnected to a backup source to maintain the time and date in the absenceof primary power The DS1302willoperate from the largerofVCC1or VCC2 When VCC2isgreater than VCC1 0 2V VCC2will power the DS1302 When VCC2isless than VCC1 VCC1will power the DS1302 SCLK Serial Clock Input SCLKisused to synchronize data movement on the serial interface I O Data Input Output The I O pinisthe bi directional data pin for the 3 wire interface RST Reset The reset signal must be asserted high during a read or a write X1 X2 Connections for a standard 32 768 kHz quartz crystal The internal oscillatorisdesigned for operation with a crystal having a specified load capacitance of 6 pF For more informationoncrystal selection and crystal layout considerations please consult Application Note 58 Crystal Considerations with Dallas RealTime Clocks The DS1302canalso be drivenbyanexternal 32 768 kHz oscillator In this configuration the X1 pinisconnected to the external oscillator signal and the X2 pinisfloated 引脚描述 VCC1 VCC1 后备电源输入端 VCC2 VCC2 主电源输入端 VCC1在缺乏主电源的情况下作为后备电源保池芯片运行和数据记录 当同时存在两个电源时 如果 VCC2比 VCC1高0 2V 则 VCC2作为电源供电 如果 VCC2低于 VCC1 则 VCC1为芯片供能 SCLK 串行时钟输入 为串行接口提供同步时钟 I O 数据输入输出 双向数据通道 RST 复位 复位芯片 读写操作中高电平有效 X1 X2 连接标准32 768KHz 晶振 晶振 6pF 的负载电容通过这两 个引脚连接内部振荡器 也可以利用外部36 768KHz 的振荡器 在这种情况下 X1连接外部振荡器并且 X2应该悬空 COMMAND BYTE The command byteisshown in Figure 2 Each data transferisinitiatedbya command byte The MSB Bit 7 must be a logic 1 Ifitis0 writes to the DS1302 will be disabled Bit 6 specifies clock calendar dataiflogic 0 or RAM dataiflogic 1 Bits 1 through 5 specify the designated registers to be input or output and the LSB bit 0 specifies a write operation input iflogic 0 or read operation output iflogic 1 The command byteisalways input starting with the LSB bit 0 指令格式 指令字节的格式如图2所示 每次数据交换总是以指令字节开始 最高 位必须为1 否则无法对芯片进行写操作 第6位指定操作的对象 0为时钟 日历 1为 RAM 第1至5位则指定要访问的寄存器 最低位指定操作的性质 0为写操 作 1为读操作 指令字节总是低位在前高位在后 RESETAND CLOCK CONTROL Alldata transfers are initiated by driving the RSTinput high TheRSTinput serves two functions First RSTturnsonthe control logic which allows access to theshiftregister for the address command sequence Second theRSTsignal provides a method of terminating either single byte or multiple byte data transfer A clock cycleisa sequence of a falling edge followedbya rising edge For data inputs data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock IftheRST inputislowalldata transfer terminates and the I O pin goes to a high impedance state Data transferisillustrated in Figure 3 At power up RSTmust be a logic 0 until VCC 2 0 volts Also SCLK must be at a logic 0 when RSTisdriven to a logic 1 state 复位和时钟控制 每次数据交换之前都需要将 RST 置高 复位信号有两种作用 第一 RST 可以打开逻辑控制器 以便允许地址 指令序列进入移位寄存器 第二 复 位信号标志着一次单字节或多字节数据交换的结束 一个时钟周期是由连续的上升沿和下降沿组成 上升沿写入数据 下降 沿输出数据 如果 RST 被拉低 那么所有数据交换都被禁止并且 I O 引脚呈现 高阻态状态 见图3 上电后在 VCC 大于2 0V 之前 RST 应该置低 RST 拉高 之后才能拉高 SCLK DATAINPUT Following the eight SCLK cycles that input a write command byte a data byteis inputonthe rising edge of the next eight SCLK cycles Additional SCLK cycles are ignored should they inadvertently occur Dataisinput starting withbit0 数据输入 一个写指令字节随着一个8时钟周期被写入 一个数据字节则在下一个8 时钟周期的上升沿写入 其它的时钟周期则视为误操作而被忽略 数据的输入格 式是低位在前 DATAOUTPUT Following the eight SCLK cycles that input a read command byte a data byteis outputonthe falling edge of the next eight SCLK cycles Note that the first databit to be transmitted occurs on the first falling edge after the lastbitofthe command byte iswritten Additional SCLK cycles retransmit the data bytes should they inadvertently occur so long as RST remains high This operation permits continuous burst mode read capability Also the I O pinistri stated upon each rising edge of SCLK Dataisoutput starting withbit0 数据输出 一个读指令操作随着一个8时钟周期被写入 一个数据字节则在下一个8 时钟周期的下降沿输出 需要注意的是 第一个数据位的传送操作是紧跟着指令 字节的最后一位被写入后执行的 只要 RST 保持高电平 SCLK 信号仍然对数 据的传送起作用 这样就使得突发模式的连续读操作变得可能 另外 I O 口在 SCLK 的上升沿处于三态 数据的输出也是从低位开始的 BURST MODE Burst mode may be specified for either the clock calendar or the RAM registers by addressing location 31 decimal address command bits 1 through 5 logic 1 As before bit6 specifies clock or RAM andbit0specifies read or write Thereis no data storage capacity at locations 9 through 31 in the Clock Calendar Registers or location 31inthe RAM registers Reads or writes in burst mode start withbit0of address 0 When writing to the clock registers in the burst mode the first eight registers must be written in order for the data to be transferred However when writing to RAM in burst modeitisnot necessary to writeall31 bytes for the data to transfer Each byte thatiswritten towillbe transferred to RAM regardless of whetherall31 bytes are written or not 突发模式 在访问时钟 日历或者 RAM 时 通过指定地址 命令字节的第1至5位全 为1来开启突发模式 和上面提到的一样 第6位指定 clock RAM 第5位指定读 写操作 在时钟 日历寄存器的第9至31位置或者 RAM 寄存器的第31位置不能存 储数据 突发模式的读写操作都是从地址0的最低位开始的 在突发模式中对 clock 寄存器写操作的时候 必须先设定头8个地址寄存器 当然 在此模式下对 RAM 写操作不是每次都必须有31字节的数据 你写的每一个字节数据都会被传 送出去 CLOCK CALENDAR The clock calendariscontained in seven write read registers as shown in Figure 4 Data contained in the clock calendar registersisinbinary coded decimal format BCD 时钟 日历 时钟日历数据都包含在七个可读写寄存器中 如表4所示 这些数据都 是用 BCD 码表示的 CLOCK HALT FLAG Bit 7ofthe seconds registerisdefined as the clock halt flag When thisbitisset to logic 1 the clock oscillatorisstopped and the DS1302isplaced into a low power standby mode with a current drain of less than 100 nanoamps When thisbitis written to logic 0 the clockwillstart The initial power on stateisnot defined 时钟停止位 秒寄存器的最高位被定义为时钟停止位 当此位置高的时候 时钟振荡 器将会停止工作并且芯片将进入低功耗等待状态 其消耗电流小于100毫微安 当此位置低的时候 时钟重新启动 AM PM 12 24MODE Bit 7ofthe hours registerisdefined as the 12 or 24 hour mode select bit When high the 12 hour modeisselected In the 12 hour mode bit5isthe AM PMbit with logic high being PM Inthe 24 hour mode bit5isthe second 10 hourbit 20 23 hours 12 24小时制 时寄存器的最高位被定义为时制选择位 1为12小时制 此时第5位为高 的话代表 PM 0为24小时制 此时第5位代表第二个10小时 20 23 小时 WRITE PROTECT BIT Bit 7ofthe control registeristhe write protect bit The first seven bits bits 0 6 are forced to 0 andwillalways read a 0 when read Before any write operation to the clock or RAM bit7 must be 0 When high the write protectbitprevents a write operation to any other register The initial poweronstateisnot defined Therefore the WPbitshould be cleared before attempting to write to the device 写保护位 控制寄存器的最高位是写保护位 该寄存器的前7位都是0 在 访问 clock 或者 RAM 之前 第7位必须为0 否则 写保护位将禁止用 户对其它寄存器写操作 因此 在对芯片写操作之前必须先声明 WP 位 TRICKLE CHARGE REGISTER This register controls the trickle charge characteristics of the DS1302 The simplified schematic of Figure 5 shows the basic componentsofthe trickle charger The trickle charge select TCS bits bits4 7 control the selection of the trickle charger In order to prevent accidental enabling only a pattern of 1010willenable the trickle charger Allother patternswilldisable the trickle charger The DS1302 powers up with the trickle charger disabled The diode select DS bits bits 2 3 select whether one diode or two diodes are connected between VCC2and VCC1 IfDSis01 one diodeisselected orifDSis10 two diodes are selected IfDSis00 or 11 the trickle chargerisdisabled independently of TCS The RS bits bits 0 1 select the resistor thatisconnected between VCC2and VCC1 The resistor selected by the resistor select RS bitsisas follows IfRSis00 the trickle chargerisdisabled independentlyofTCS Diode and resistor selectionisdeterminedbythe user according to the maximum current desired for battery or super cap charging The maximum charging current can be calculated as illustrated in the following example Assume that a system power supplyof5 voltisapplied to VCC2 and a super capisconnected to VCC1 Also assume that the trickle charger has been enabled with one diode and resistor R1 between VCC2and VCC1 The maximum current Imax would therefore be calculated as follows Imax 5 0V diode drop R1 5 0V 0 7V 2 k 2 2 mA Obviously as the super cap charges the voltage drop between VCC2and VCC1 willdecrease and therefore the charge currentwilldecrease 涓流充电寄存器 该寄存器控制着芯片的涓流充电 其结构简图见图5 TCS 位控制着涓 流充电的选择 为了防止意外操作 设定为只有1010能开启 其它的均为无效操 作 芯片上电时 涓流充电不工作 DS 位决定接入 VCC1和 VCC2之间的二极 管数量 DS 为01时 接入1个二极管 为10时 接入2个 如果 DS 为00或者11 涓流充电不能开启 而 RS 位决定接入 VCC1和 VCC2之间的电阻值 具体参数 如表所示 如果 RS 为00 涓流充电也不能开启 用户根据电池或者超级电容的设计选择二极管和电阻的接入 从而决定 最大电流 最大充电电流的计算可以参考下面的例子 如果一个5V 的供电系统 接入 VCC2 一个超级电容接在 VCC1 同时假设涓流充电已开启并且在 VCC1 和 VCC2之间接入1个二极管和 R1电阻 那么最大电流的计算如下所示 Imax 5 0V 二极管压降 R1 5 0V 0 7V 2 k 2 2 mA 显然 由于超级电容的存在 VCC1和 VCC2之间的压降减小了 因此 电流也减小了 CLOCK CALENDAR BURST MODE The clock calendar command byte specifies burst mode operation In this mode the first eight clock calendar registers can be consecutively read or written see Figure 4 starting withbit0 of address 0 Ifthe write protectbitisset high when a write clock calendar burst modeisspecified no data transferwilloccur to anyofthe eight clock calendar registers this includes the control register The trickle chargerisnot accessible in burst mode Atthe beginning of a clock burst read the current timeis transferred to a second set of registers The time informationisread from the