8位数码显示频率计设计.doc

FPGA实验实验三实验目的： 设计8位频率计，学习较复杂的数字系统的设计方法。实验原理及内容： 根据频率的定义和频率测量的基本原理。 测定信号的频率必须有一个脉宽为1秒的输入信号脉冲计数允许的信号；1秒计数结束后，计数值被锁入锁存器，计数器清零，为下一测频计数周期作好准备。实验步骤： 1.设计生成1秒时钟信号- CLK 2.设计测频控制信号发生器- FTCTRL; 3.设计1秒计数值锁存器 - REG32B; 4.设计32位二进制计数器- COUNTER32B 5.设计十六进制7段译码器- Decoder 6.设计生成1KHz或10KHz待测信号- Fin 7.完成频率计设计、仿真和硬件实现。 实验内容：module pinlu(clock,z0,z1,z2,z3,z4,z5,z6,z7);input clock;output6:0 z0;output6:0 z1;output6:0 z2;output6:0 z3;output6:0 z4;output6:0 z5;output6:0 z6;output6:0 z7;reg clk;reg fin;reg rst;reg en=1b0;reg load=1b1;reg 25:0k;reg 25:0f;reg 31:0C;reg 31:0x=32b0;reg 6:0z0,z1,z2,z3,z4,z5,z6,z7;always(posedge clock)begin if(k=26d25000000) begin clk=1b1; k=0; end else begin clk=1b0; k=k+1; endend always(posedge clock)begin if(f=26d2500) begin fin=1b1; f=0; end else begin fin=1b0; f=f+1; endendalways(posedge clk) begin load=load; en=en; endalways(clk or en or load )beginif(clk=1b0&en=1b0&load=1b1) rst=1b1;else rst=1b0;endalways(posedge rst or posedge fin)beginif(rst)C=32b0;elseif(en)C=C+1b1;endalways (posedge load)beginx=C;endalways(x)begin case (x3:0) 4b0000:z0=7b1000000; 4b0001:z0=7b1111001; 4b0010:z0=7b0100100; 4b0011:z0=7b0110000; 4b0100:z0=7b0011001; 4b0101:z0=7b0010010; 4b0110:z0=7b0000010; 4b0111:z0=7b1111000; 4b1000:z0=7b0000000; 4b1001:z0=7b0001001; 4b1010:z0=7b0001000; 4b1011:z0=7b0000011; 4b1100:z0=7b1000110; 4b1101:z0=7b0100001; 4b1110:z0=7b0000110; 4b1111:z0=7b0001110; default : z0=7b0000001; endcase case (x7:4) 4b0000:z1=7b1000000; 4b0001:z1=7b1111001; 4b0010:z1=7b0100100; 4b0011:z1=7b0110000; 4b0100:z1=7b0011001; 4b0101:z1=7b0010010; 4b0110:z1=7b0000010; 4b0111:z1=7b1111000; 4b1000:z1=7b0000000; 4b1001:z1=7b0001001; 4b1010:z1=7b0001000; 4b1011:z1=7b0000011; 4b1100:z1=7b1000110; 4b1101:z1=7b0100001; 4b1110:z1=7b0000110; 4b1111:z1=7b0001110; default : z1=7b0000001; endcase case (x11:8) 4b0000:z2=7b1000000; 4b0001:z2=7b1111001; 4b0010:z2=7b0100100; 4b0011:z2=7b0110000; 4b0100:z2=7b0011001; 4b0101:z2=7b0010010; 4b0110:z2=7b0000010; 4b0111:z2=7b1111000; 4b1000:z2=7b0000000; 4b1001:z2=7b0001001; 4b1010:z2=7b0001000; 4b1011:z2=7b0000011; 4b1100:z2=7b1000110; 4b1101:z2=7b0100001; 4b1110:z2=7b0000110; 4b1111:z2=7b0001110; default : z2=7b0000001; endcase case (x15:12) 4b0000:z3=7b1000000; 4b0001:z3=7b1111001; 4b0010:z3=7b0100100; 4b0011:z3=7b0110000; 4b0100:z3=7b0011001; 4b0101:z3=7b0010010; 4b0110:z3=7b0000010; 4b0111:z3=7b1111000; 4b1000:z3=7b0000000; 4b1001:z3=7b0001001; 4b1010:z3=7b0001000; 4b1011:z3=7b0000011; 4b1100:z3=7b1000110; 4b1101:z3=7b0100001; 4b1110:z3=7b0000110; 4b1111:z3=7b0001110; default : z3=7b0000001; endcase case (x19:16) 4b0000:z4=7b1000000; 4b0001:z4=7b1111001; 4b0010:z4=7b0100100; 4b0011:z4=7b0110000; 4b0100:z4=7b0011001; 4b0101:z4=7b0010010; 4b0110:z4=7b0000010; 4b0111:z4=7b1111000; 4b1000:z4=7b0000000; 4b1001:z4=7b0001001; 4b1010:z4=7b0001000; 4b1011:z4=7b0000011; 4b1100:z4=7b1000110; 4b1101:z4=7b0100001; 4b1110:z4=7b0000110; 4b1111:z4=7b0001110; default : z4=7b0000001; endcase case (x23:20) 4b0000:z5=7b1000000; 4b0001:z5=7b1111001; 4b0010:z5=7b0100100; 4b0011:z5=7b0110000; 4b0100:z5=7b0011001; 4b0101:z5=7b0010010; 4b0110:z5=7b0000010; 4b0111:z5=7b1111000; 4b1000:z5=7b0000000; 4b1001:z5=7b0001001; 4b1010:z5=7b0001000; 4b1011:z5=7b0000011; 4b1100:z5=7b1000110; 4b1101:z5=7b0100001; 4b1110:z5=7b0000110; 4b1111:z5=7b0001110; default : z5=7b0000001; endcase case (x27:24) 4b0000:z6=7b1000000; 4b0001:z6=7b1111001; 4b0010:z6=7b0100100; 4b0011:z6=7b0110000; 4b0100:z6=7b0011001; 4b0101:z6=7b0010010; 4b0110:z6=7b0000010; 4b0111:z6=7b1111000; 4b1000:z6=7b0000000; 4b1001:z6=7b0001001; 4b1010:z6=7b0001000; 4b1011:z6=7b0000011; 4b1100:z6=7b1000110; 4b1101:z6=7b0100001; 4b1110:z6=7b0000110; 4b1111:z6=7b0001110; default : z6=7b0000001; endcase case (x31:28) 4b0000:z7=7b1000000; 4b0001:z7=7b1111001; 4b0010:z7=7b0100100; 4b0011:z7=7b0110000; 4b0100:z7=7b0011001; 4b0101:z7=7b0010010; 4b0110:z7=7b0000010; 4b0111:z7=7b1111000; 4b1000:z7=7b