FPGA程序乘法器.doc

乘法器：by leasualmodule mui44(a,b,rst,out,bai,shi,ge);input rst;input3:0a,b; output out,bai,shi,ge;reg3:0bai,shi,ge;wire7:0out1,out2,out3,out4;reg7:0out;always (*) if(!rst) begin out=0; bai=0; shi=0; ge=0; end else begin out=out1+out2+out3+out4; bai=out/100; shi=out%100/10; ge=out%10; endassign out1=(b0=1)?a:0;assign out2=(b1=1)?(a1):0;assign out3=(b2=1)?(a2):0;assign out4=(b3=1)?(a3):0;endmodule奇数分频：by leasualmodule jishufenp(rst,clk,clkout); parameter N=3;/计数器的位数 N的最大计数值要大于或等于M parameter M=7; /要分频的模，取奇数 input rst; input clk; output clkout; reg tempp,tempn; reg N-1:0 count; always (negedge rst or posedge clk) if(!rst) begin count=0; tempp=0; end else begin count=count+1; if(count=M/2) tempp=1; else if(count=M-1) begin tempp=0; count=0; end end always (negedge rst or negedge clk) if(!rst) tempn=0; else tempn=tempp; assign clkout=tempp|tempn; endmodule状态机：/*gongneng: jian ce xulie 1011 chengxuby leasual2010.11.29*/module ztj2(a,rst,clk,q);input clk,a,rst;output q;reg q;reg7:0 cur_state;parameter s1=8b0000_0001,s2=8b0000_0010,s3=8b0000_0100,s4=8b0000_1000,s5=8b0001_0000,s6=8b0010_0000,s7=8b0100_0000,s8=8b1000_0000;always(posedge clk or negedge rst)if(rst)begincur_state=s1;end elsecase(cur_state)s1:begincur_state=(a=1)?s2:s1);q=0;ends2:begincur_state=(a=0)?s3:s2);q=0;ends3:begincur_state=(a=1)?s4:s1);q=0;ends4:begincur_state=(a=1)?s5:s3);q=0;ends5:begincur_state=(a=0)?s6:s2);q=0;ends6:begincur_state=(a=1)?s7:s1);q=0;ends7:begincur_state=(a=0)?s8:s5);q=0;ends8:if(a=1)begincur_state=s1;q=1;en