ARM学习经验_UART串口无法正确输出字符.doc

UART串口无法正确输出字符使用.s文件进行初始化设置，程序代码如下：; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRsMode_USR EQU 0x10Mode_FIQ EQU 0x11Mode_IRQ EQU 0x12Mode_SVC EQU 0x13Mode_ABT EQU 0x17Mode_UND EQU 0x1BMode_SYS EQU 0x1FI_Bit EQU 0x80 ; when I bit is set, IRQ is disabledF_Bit EQU 0x40 ; when F bit is set, FIQ is disabledUND_Stack_Size EQU 0x00000000SVC_Stack_Size EQU 0x00000080ABT_Stack_Size EQU 0x00000000FIQ_Stack_Size EQU 0x00000000IRQ_Stack_Size EQU 0x00000100USR_Stack_Size EQU 0x00000400ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) AREA STACK, NOINIT, READWRITE, ALIGN=3Stack_Mem SPACE USR_Stack_Size_initial_sp SPACE ISR_Stack_SizeStack_TopHeap_Size EQU 0x00000000 AREA HEAP, NOINIT, READWRITE, ALIGN=3_heap_baseHeap_Mem SPACE Heap_Size_heap_limit; System Control Unit (SCU) definitionsSCU_BASE EQU 0x5C002000 ; SCU Base Address (non-buffered)SCU_CLKCNTR_OFS EQU 0x00 ; Clock Control register OffsetSCU_PLLCONF_OFS EQU 0x04 ; PLL Configuration register OffsetSCU_SYSSTAT_OFS EQU 0x08 ; System Status Register OffsetSCU_PCGR0_OFS EQU 0x14 ; Peripheral Clock Gating Register 0 OffsetSCU_PCGR1_OFS EQU 0x18 ; Peripheral Clock Gating Register 1 OffsetSCU_PRR0_OFS EQU 0x1C ; Peripheral Reset Register 0 OffsetSCU_PRR1_OFS EQU 0x20 ; Peripheral Reset Register 1 OffsetSCU_SCR0_OFS EQU 0x34 ; System Configuration Register 0 OffsetSCU_PECGR0_OFS EQU 0x2CSCU_PECGR1_OFS EQU 0x30SCU_GPIOOUT0_OFS EQU 0x44SCU_GPIOOUT1_OFS EQU 0x48SCU_GPIOOUT2_OFS EQU 0x4CSCU_GPIOOUT3_OFS EQU 0x50SCU_GPIOOUT4_OFS EQU 0x54SCU_GPIOOUT5_OFS EQU 0x58SCU_GPIOOUT6_OFS EQU 0x5CSCU_GPIOOUT7_OFS EQU 0x60SCU_GPIOIN0_OFS EQU 0x64SCU_GPIOIN1_OFS EQU 0x68SCU_GPIOIN2_OFS EQU 0x6CSCU_GPIOIN3_OFS EQU 0x70SCU_GPIOIN4_OFS EQU 0x74SCU_GPIOIN5_OFS EQU 0x78SCU_GPIOIN6_OFS EQU 0x7CSCU_GPIOIN7_OFS EQU 0x80SCU_GPIOTYPE0_OFS EQU 0x84SCU_GPIOTYPE1_OFS EQU 0x88SCU_GPIOTYPE2_OFS EQU 0x8CSCU_GPIOTYPE3_OFS EQU 0x90SCU_GPIOTYPE4_OFS EQU 0x94SCU_GPIOTYPE5_OFS EQU 0x98SCU_GPIOTYPE6_OFS EQU 0x9CSCU_GPIOTYPE7_OFS EQU 0xA0SCU_GPIOTYPE8_OFS EQU 0xA4SCU_GPIOTYPE9_OFS EQU 0xA8SCU_GPIOEMI_OFS EQU 0xACSCU_WKUPSEL_OFS EQU 0xB0SCU_GPIOANA_OFS EQU 0xBCGPIO3_BASE EQU 0x58009000GPIO_DIR_OFS EQU 0x400GPIO_SEL_OFS EQU 0x420UART0_BASE EQU 0x5C004000UART1_BASE EQU 0x5C005000UART_FR_OFS EQU 0x18UART_ILPR_OFS EQU 0x20 UART_IBRD_OFS EQU 0x24 UART_FBRD_OFS EQU 0x28 UART_LCR_OFS EQU 0x2C UART_CR_OFS EQU 0x30 UART_IFLS_OFS EQU 0x34 UART_IMSC_OFS EQU 0x38UART_ICR_OFS EQU 0x44 UART_DMACR_OFS EQU 0x48; ConstantsSYSSTAT_LOCK EQU 0x01 ; PLL Lock Status; Flash Memory Interface (FMI) definitions (Flash banks sizes and addresses)FMI_BASE EQU 0x54000000 ; FMI Base Address (non-buffered)FMI_BBSR_OFS EQU 0x00 ; Boot Bank Size RegisterFMI_NBBSR_OFS EQU 0x04 ; Non-boot Bank Size RegisterFMI_BBADR_OFS EQU 0x0C ; Boot Bank Base Address RegisterFMI_NBBADR_OFS EQU 0x10 ; Non-boot Bank Base Address RegisterFMI_CR_OFS EQU 0x18 ; Control Register; APB Bridge 1 & 2 definitions (Peripherals)APB0_BUF_BASE EQU 0x48001802 ; APB Bridge 0 Buffered Base AddressAPB0_NBUF_BASE EQU 0x58000000 ; APB Bridge 0 Non-buffered Base AddressAPB1_BUF_BASE EQU 0x4C000000 ; APB Bridge 1 Buffered Base AddressAPB1_NBUF_BASE EQU 0x5C000000 ; APB Bridge 1 Non-buffered Base AddressFMI_CR_Val EQU 0x00000018 ;0FMI_BBSR_Val EQU 0x00000004 ;1FMI_BBADR_Val EQU 0x00000000 ;2FMI_NBBSR_Val EQU 0x00000002 ;3FMI_NBBADR_Val EQU 0x00400000 ;4FLASH_CFG_Val EQU 0x00000000 ;5STARTUPEQU1;0SCU_CLKCNTR_Val EQU 0x00031404 ;1SCU_PLLCONF_Val EQU 0x000BC019 ;2SCU_SYSSTATUS_Val EQU 0x0000003F ;3SCU_PWRMNG_Val EQU 0x00000000 ;4SCU_ITCMSK_Val EQU 0x00000001 ;5SCU_PCGR0_Val EQU 0x000000FB ;6SCU_PCGR1_Val EQU 0x01FFCC39 ;7SCU_PRR0_Val EQU 0x00001873 ;8SCU_PRR1_Val EQU 0x00FEC839 ;9SCU_MGR0_Val EQU 0x00000000 ;10SCU_MGR1_Val EQU 0x00000000 ;11SCU_PECGR0_Val EQU 0x00000000 ;12SCU_PECGR1_Val EQU 0x00000000 ;13SCU_SCR0_Val EQU 0x000000B1 ;14SCU_WKUPSEL_Val EQU 0x00000000 ;15SCU_GPIOOUT0_Val EQU 0x00000000 ;0SCU_GPIOOUT1_Val EQU 0x00000000 ;1SCU_GPIOOUT2_Val EQU 0x00000000 ;2SCU_GPIOOUT3_Val EQU 0x00000008 ;3SCU_GPIOOUT4_Val EQU 0x00000000 ;4SCU_GPIOOUT5_Val EQU 0x0000FFA8 ;5SCU_GPIOOUT6_Val EQU 0x00000000 ;6SCU_GPIOOUT7_Val EQU 0x0000EAAA ;7SCU_GPIOIN0_Val EQU 0x00000000 ;8SCU_GPIOIN1_Val EQU 0x00000000 ;9SCU_GPIOIN2_Val EQU 0x00000000 ;10SCU_GPIOIN3_Val EQU 0x00000001 ;11SCU_GPIOIN4_Val EQU 0x00000000 ;12SCU_GPIOIN5_Val EQU 0x00000000 ;13SCU_GPIOIN6_Val EQU 0x00000000 ;14SCU_GPIOIN7_Val EQU 0x00000000 ;15SCU_GPIOTYPE0_Val EQU 0x00000000 ;16SCU_GPIOTYPE1_Val EQU 0x00000000 ;17SCU_GPIOTYPE2_Val EQU 0x00000000 ;18SCU_GPIOTYPE3_Val EQU 0x00000000 ;19SCU_GPIOTYPE4_Val EQU 0x00000000 ;20SCU_GPIOTYPE5_Val EQU 0x00000000 ;21SCU_GPIOTYPE6_Val EQU 0x00000000 ;22SCU_GPIOTYPE7_Val EQU 0x00000000 ;23SCU_GPIOTYPE8_Val EQU 0x00000000 ;24SCU_GPIOTYPE9_Val EQU 0x00000000 ;25SCU_GPIOANA_Val EQU 0x00000000 ;26GPIO0_DIR_Val EQU 0X00 ;27GPIO1_DIR_Val EQU 0X00 ;28GPIO2_DIR_Val EQU 0X00 ;29GPIO3_DIR_Val EQU 0X0A ;30GPIO4_DIR_Val EQU 0X00 ;31GPIO5_DIR_Val EQU 0X00 ;32GPIO6_DIR_Val EQU 0X00 ;33GPIO7_DIR_Val EQU 0X00 ;34GPIO0_SEL_Val EQU 0X00 ;35GPIO1_SEL_Val EQU 0X00 ;36GPIO2_SEL_Val EQU 0X00 ;37GPIO3_SEL_Val EQU 0X00 ;38GPIO4_SEL_Val EQU 0X00 ;39GPIO5_SEL_Val EQU 0X00 ;40GPIO6_SEL_Val EQU 0X00 ;41GPIO7_SEL_Val EQU 0X00 ;42RTC_TR_Val EQU 0x14100930 ;0RTC_DTR_Val EQU 0x20110301 ;1RTC_ATR_Val EQU 0x00000000 ;2RTC_CR_Val EQU 0x00000000 ;3RTC_MILR_Val EQU 0x00000000 ;4UART0_ILPR_Val EQU 0x0034 ;0UART0_IBRD_Val EQU 0x004E ;1UART0_FBRD_Val EQU 0x0008 ;2UART0_LCR_Val EQU 0x0060 ;3UART0_CR_Val EQU 0x0301 ;4UART0_IFLS_Val EQU 0x0012 ;5UART0_IMSC_Val EQU 0x0030 ;6UART0_ICR_Val EQU 0x0010 ;7UART0_DMACR_Val EQU 0x0000 ;8UART1_ILPR_Val EQU 0x0034 ;0UART1_IBRD_Val EQU 0x0138 ;1UART1_FBRD_Val EQU 0x0020 ;2UART1_LCR_Val EQU 0x0070 ;3UART1_CR_Val EQU 0x0301 ;4UART1_IFLS_Val EQU 0x0012 ;5UART1_IMSC_Val EQU 0x0010 ;6UART1_ICR_Val EQU 0x0010 ;7UART1_DMACR_Val EQU 0x0000 ;8UART2_ILPR_Val EQU 0x000C ;0UART2_IBRD_Val EQU 0x004E ;1UART2_FBRD_Val EQU 0x0008 ;2UART2_LCR_Val EQU 0x0060 ;3UART2_CR_Val EQU 0x0301 ;4UART2_IFLS_Val EQU 0x0012 ;5UART2_IMSC_Val EQU 0x0030 ;6UART2_ICR_Val EQU 0x0010 ;7UART2_DMACR_Val EQU 0x0000 ;8;/ System Ctrl;/ Setup System Configuration (and SRAM Size);/ ;/ Setup Flash Memory Interface (FMI);/ ;/ Setup Clock;/ ;/ Setup Peripheral Rese;/ ;/ Setup Library Exception Handlers;/ ;/ Setup Controller area network (CAN);/ ;/ Setup External Memory Interface(EMI);/ ;/ Setup Vectored interrupt controller (VIC);/ ;/ Setup Universal asynchronous receiver transmitter (UART);/ ;/ Setup General purpose I/O ports (GPIO);/ ;/ Setup Real time clock (RTC);/ ;/ Setup 16-bit timer (TIM);/ ;/ SCR0_SETUP EQU 1 ;0FMI_SETUP EQU 1 ;1CLOCK_SETUP EQU 1 ;2 P_RESET_SETUPEQU 1 ;3LEH_SETUP EQU 0 ;4CAN_SETUP EQU 0 ;5EMI_SETUP EQU 0 ;6VIC_SETUP EQU 0 ;7UART_SETUP EQU 1 ;8GPIO_SETUP EQU 1 ;9RTC_SETUP EQU 0 ;10TIM_SETUP EQU 0 ;11;T_Bit EQU 0x20 PRESERVE8; Area Definition and Entry Point; Startup Code must be linked first at Address at which it expects to run. AREA Reset, CODE, READONLY ARM; Exception Vectors; Mapped to Address 0.; Absolute addressing mode must be used.; Dummy Handlers are implemented as infinite loops which can be modified.Vectors LDR PC, Reset_Addr LDR PC, Undef_Addr LDR PC, SWI_Addr LDR PC, PAbt_Addr LDR PC, DAbt_Addr NOP ; Reserved Vector ; LDR PC, IRQ_Addr LDR PC, PC, #-0x0FF0 LDR PC, FIQ_Addr IF LEH_SETUP 0 EXTERN UndefHandler EXTERN SWIHandler EXTERN PAbtHandler EXTERN DAbtHandler EXTERN IRQHandler EXTERN FIQHandler ENDIF Reset_Addr DCD Reset_HandlerUndef_Addr DCD UndefHandlerSWI_Addr DCD SWI_HandlerPAbt_Addr DCD PAbtHandlerDAbt_Addr DCD DAbtHandler DCD 0 ; Reserved Address IRQ_Addr DCD IRQHandlerFIQ_Addr DCD FIQHandler IF LEH_SETUP = 0 IMPORT SWI_Handler ; SWI.s UndefHandler B UndefHandler;SWIHandler B SWIHandlerPAbtHandler B PAbtHandlerDAbtHandler B DAbtHandlerIRQHandler B IRQHandlerFIQHandler B FIQHandler ENDIF; Reset Handler EXPORT Reset_HandlerReset_Handler NOP ; Wait for OSC stabilization NOP NOP NOP NOP NOP NOP NOP; Setup System Configuration (and SRAM Size) IF SCR0_SETUP = 1 LDR R0, =SCU_BASE LDR R1, =SCU_SCR0_Val STR R1, R0, #SCU_SCR0_OFSORR R1, #0x00000200 STR R1, R0, #SCU_SCR0_OFS ENDIF; Setup Flash Memory Interface (FMI) IF FMI_SETUP = 1 LDR R0, =FMI_BASE LDR R1, =FMI_BBSR_Val STR R1, R0, #FMI_BBSR_OFS LDR R1, =FMI_NBBSR_Val STR R1, R0, #FMI_NBBSR_OFS LDR R1, =(FMI_BBADR_Val:SHR:2) STR R1, R0, #FMI_BBADR_OFS LDR R2, =(FMI_NBBADR_Val:SHR:2) STR R2, R0, #FMI_NBBADR_OFS LDR R3, =FMI_CR_Val STR R3, R0, #FMI_CR_OFS ; Write Write flash configuration command (60h) ; IF :DEF:BOOT_BANK1 MOV R0, R1, LSL #2; ELSE; MOV R0, R2, LSL #2; ENDIF MOV R1, #0x60 STRH R1, R0, #0 ; Write Write flash configuration confirm command (03h) LDR R2, =(FLASH_CFG_Val:SHL:2) ADD R0, R0, R2 MOV R1, #0x03 STRH R1, R0, #0 ENDIF; Setup Clock IF CLOCK_SETUP = 1 LDR R0, =SCU_BASE;LDR R1, =SCU_SYSSTATUS_Val; STR R1, R0, #SCU_SYSSTAT_OFS;Clear flag LDR R1, =0x00020002 STR R1, R0, #SCU_CLKCNTR_OFS ; Select OSC as clk src NOP ; Wait for OSC stabilization NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP LDR R1, =0x0003C019 ; PLL to default STR R1, R0, #SCU_PLLCONF_OFS LDR R1, =SCU_PLLCONF_Val ; PLL to requested value STR R1, R0, #SCU_PLLCONF_OFS ; Wait until PLL is stabilized (if PLL enabled) IF (SCU_PLLCONF_Val:AND:0x80000) != 0PLL_Loop LDR R2, R0, #SCU_SYSSTAT_OFS ANDS R2, R2, #SYSSTAT_LOCK BEQ PLL_Loop ENDIF LDR R1, =SCU_CLKCNTR_Val ; Setup clock control STR R1, R0, #SCU_CLKCNTR_OFS LDR R1, =SCU_PCGR0_Val ; Enable clock gating STR R1, R0, #SCU_PCGR0_OFS LDR R1, =SCU_PCGR1_Val STR R1, R0, #SCU_PCGR1_OFS ENDIF; Setup Peripheral Reset IF P_RESET_SETUP != 0 LDR R1, =SCU_PRR0_Val STR R1, R0, #SCU_PRR0_OFS LDR R1, =SCU_PRR1_Val STR R1, R0, #SCU_PRR1_OFS ENDIF; Setup Stack for each mode LDR R0, =Stack_Top; Enter Undefined Instruction Mode and set its Stack Pointer MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #UND_Stack_Size; Enter Abort Mode and set its Stack Pointer MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #ABT_Stack_Size; Enter FIQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #FIQ_Stack_Size; Enter IRQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #IRQ_Stack_Size; Enter Supervisor Mode and set its Stack Pointer MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #SVC_Stack_Size; Enter User Mode and set its Stack Pointer MSR CPSR_c, #Mode_USR ; IF :DEF:_MICROLIB ; EXPORT _initial_sp; ELSE MOV SP, R0 SUB SL, SP, #USR_Stack_Size; ENDIF; Setup General purpose I/O ports (GPIO)IF GPIO_SETUP = 1IF (SCU_PCGR1_Val:AND:0x20000) != 0 ;SET GPIO3LDR R0, =GPIO3_BASELDR R1,=GPIO3_DIR_ValSTR R1, R0, #GPIO_DIR_OFSLDR R1,=GPIO3_SEL_ValSTR R1, R0, #GPIO_SEL_OFSLDR R0, =SCU_BASELDR R1,=SCU_GPIOOUT3_ValSTR R1, R0, #SCU_GPIOOUT3_OFSLDR R1,=SCU_GPIOIN3_ValSTR R1, R0, #SCU_GPIOIN3_OFSLDR R1,=SCU_GPIOTYPE3_ValSTR R1, R0, #SCU_GPIOTYPE3_OFSENDIFENDIF; Setup Universal asynchronous receiver transmitter (UART) IF UART_SETUP != 0 IF (SCU_PCGR1_Val:AND:0x8) != 0 ;SET UART0LDR R0, =UART0_BASELDR R1,=0x0300STR R1, R0, #UART_CR_OFS ;STOP UART0 UART0_Loop LDR R2, R0, #UART_FR_OFS ANDS R2, R2, #0x8CMPR2,#0x8 BEQ UART0_Loop ;wait for UART0 freeLDR R1,=0x0000STR R1, R0, #UART_LCR_OFS ;close FIFOLDR R1,=UART0_IBRD_ValSTR R1, R0, #UART_IBRD_OFSLDR R1,=UART0_FBRD_ValSTR R1, R0, #UART_FBRD_OFSLDR R1,=UART0_IFLS_ValSTR R1, R0, #UART_IFLS_OFSLDR R1,=UART0_IMSC_ValSTR R1, R0, #UART_IMSC_OFS LDR R1,=UART0_ICR_ValSTR R1, R0, #UART_ICR_