FPGA 驱动触摸屏(TFT).doc

FPGA 驱动触摸屏(TFT)发表于 2010 年 09 月 07 日 由 hulin 1,830 views 可视化的操作已经广泛的深入我们的生活方方面面了，自己在做一些项目和实验都要用到可视化。我这儿把ALTERA公司的飓风二系列中的ep2c5接上触摸屏，本来是R7:0，G7:0和B7:0。也就是一个像素的数据量就是3字节，但由于很多DSP或者单片机数据总线格式一般是16bit和32bit。本人在这儿使用16bit，根据人的视觉感受，我们把24bit抽取出16bit。格式为pixdata15:0=R7:3,G7:2,B7:3取其每个色相的高位（取R高5位，取G高6位，取B高5位，组成RBG565格式）。虽然在每一个像素都有色相不全，但是这样基本能显示所有的图片。FPGA的程序模块根据TFT LCD的显示控制时序编写Verilog代码，以实现显示图片的功能。其时序如图：一、FPGA LCD显示模块的Verilog代码：module TftControl( / inputs reset, tftcs, clk,R_in,G_in,B_in,/outputshsync,vsync,R,G,B,pixclk,tften,startpicture,pictureclk);/inputsinput reset;input tftcs;input clk;input 4:0 R_in;input 5:0 G_in;input 4:0 B_in;/outputsoutput hsync;output vsync;output 4:0 R;output 5:0 G;output 4:0 B;output startpicture;output pictureclk;output pixclk;output tften;wire hsync;wire vsync;wire startpicture;reg tften;reg 4:0 R;reg 5:0 G;reg 4:0 B;reg pixclk;reg pictureclk;reg 10:0 pix_count;reg 10:0 line_count;reg 2:0 counter;/ 320 by 240 VGA timing parameters/ horizontal timing parametersparameter hsync_end = 30; /sync pulse, 320240 = 96parameter hblank_begin = 68; / = sync + back porch, 320240 = 68parameter hblank_end = 388; / = sync + back porch + h_resolution, 320240 = 388parameter hline_end = 408; / = sync + back porch + h_resolution + front porch, 320240 = 408/ vertical timing parametersparameter vsync_end = 3; /sync pulse, 320240 = 3parameter vblank_begin = 18; / = sync + back porch, 320240 = 18parameter vblank_end = 258; / = sync + back porch + v_resolution, 320240 = 258parameter vframe_end = 262; / = sync + back porch + v_resolution + front porch, 320240 = 262/ these are all the syncs and blanks for the video timingassign hsync = (pix_count hsync_end) ? 1b0 : 1b1;assign vsync = (line_count (vblank_begin-1) & (line_count (hblank_begin 1) & (pix_count (hblank_end) ? 1b1 : 1b0;always (posedge clk)begin if (!reset) begin counter=0; tften=1; end else if(!tftcs) begin tften=0; counter=counter+1; pixclk=counter2; R = (startpicture) ? R_in : 5h00; / red color value output to video DAC G = (startpicture) ? G_in : 6h00; / green color value output to video DAC B = (startpicture) ? B_in : 5h00; / blue color value output to video DAC pictureclk=(startpicture) ? counter2:1bz ; end else begin tften=1;R = 5hzz; / red color value output to video DAC G = 6hzz; / green color value output to video DAC B = 5hzz; / blue color value output to video DACendend/ the heart of the time base these two counters, the pixel and line countersalways (posedge pixclk)begin if (!reset) begin pix_count = 11h0;line_count = 11h0;endelse begin if(pix_count = (hline_end-1) begin pix_count = 11h0; if(line_count = (vframe_end-1) begin line_count = 11h0;end else begin line_count = line_count + 1b1;endendelse begin pix_count = pix_count + 1b1;end endendendmodule 触摸屏输入由于面板上的触摸屏产生的输出信号不是直接的数字电平，其产生的为模拟电压。通过压力传感电阻把触摸笔在面板上的位置通过传感电阻转换成不同的电压值通过+X，+Y,-X,-Y四个脚输出模拟信号。如图所示：电阻式触摸屏专用控制器ADS7843的应用就构成了集文字图形笔输入控制、编辑和无线传送于一体的无线掌上电脑产品。ADS7843是BURR-BROWN公司专用于4线电阻式触摸屏的12位模/数采样转换器，单一电源供电、完全降功耗模式、转换速度快。ADS7843大量用在电池供电PDA（personaldigitalassistants）和手持便携式装置中。通过FPGA IO脚对ADS7843进行接口控制就能获取触摸屏位置转换信号，FPGA作为液晶显示控制器就能将显示缓冲区数据送到液晶屏上正确显示。二、FPGA触摸输入Verilog程序：module TouchControl(mclk,rst,csn,dclk,din,dout,busy,tint, datareg,datax1,datax2,datay1,datay2,LCD_POWERON,dout_en);input mclk,rst,dout,busy,tint;output csn,dclk,din;output 11:0datareg,datax1,datax2,datay1,datay2;output wire LCD_POWERON=1bz;output dout_en;reg 10:0 clkcnt;always (posedge mclk or negedge rst) if(!rst) clkcnt=11d0; else clkcnt=clkcnt+1b1;wire clk_32=clkcnt9;reg 5:0 state;reg csn,flagxy,startflag;reg 1:0 cnty;reg 3:0 cmdx,waitdin,waitdin2;reg 7:0 cmd;reg 9:0 tintflag;reg din;reg 19:0 endcnt;wire dclk=(!csn)?clk_32:1b0;always (negedge clk_32 or negedge rst) if(!rst) begin state=6d0;csn=1b1;cmdx=4d0;din=1b0;waitdin=4d0;flagxy=1b0;cnty=2d0; waitdin2=4d0;startflag=1b0;endcnt=20d0;endelse case(state) 6d0: begin state=6d1; end 6d1: begin if(!tint) state=6d2;else state=state; end 6d2:begincmd=8b10010000;state=3d3; end 6d3: begin csn=1b0;if(cmdx!=4d7) begin din=cmd7; cmd=(cmd1); cmdx=cmdx+1b1; state=state;end else begin din=cmd7; cmdx=4d0; case(cnty) 2d0: begin cmd=8b11010000;cnty=2d1;state=6d4; end2d1: begincmd=8b10010000;cnty=2d2; state=6d4; end 2d2:begincmd=8b11010000; cnty=2d3; state=6d4; end 2d3: begincnty=2d0; state=6d5; end endcase end end6d4:begin if(waitdin!=4d15)begin waitdin=waitdin+1b1;din=1b0;state=state; end else begin waitdin=4d0;din=1b0; state=3d3; endend6d5:begin if(waitdin2!=4d15)begin waitdin2=waitdin2+1b1; state=state;endelse begin waitdin2=4d0; csn=1b1;state=6d6;/if(!startflag) begin state=6d1;startflag=1b1;end/else begin state=6d1;startflag=1b0;endendend6d6:beginif(endcnt=20d10000) begin endcnt=20d0;state=6d1; end else begin endcnt=endcnt+1b1;state=state; end endendcasereg 11:0 datareg,datax1,datax2,datay1,datay2;reg 3:0 readcnt,statedin,readxy;reg dout_en;always (posedge dclk or negedge rst) if(!rst) begin datareg=12d0;datax1=12d0;datax2=12d0;datay1=12d0;datay2=12d0;readcnt=4d0;statedin=4d0;readxy=4d0;dout_en=1b1; end else begin case(statedin) 4d0: begin dout_en=1b1; if(busy) begin datareg=12d0;statedin=4d1;end else statedin=statedin; end 4d1: begin case(readcnt)4d0:begin datareg11=dout;readcnt=4d1;statedin=statedin;end4d1:begin datareg10=dout;readcnt=4d2;statedin=statedin;end 4d2:begin datareg9 =dout;readcnt=4d3;statedin=statedin;end4d3:begin datareg8 =dout;readcnt=4d4;statedin=statedin;end 4d4:begin datareg7 =dout;readcnt=4d5;statedin=statedin;end 4d5:begin datareg6 =dout;readcnt=4d6;statedin=statedin;end4d6:begin datareg5 =dout;re