DE2实验练习解答—lab6Adders.doc

/halflife/archive/2010/07/05/1771746.html本练习的目的是实现算术运算电路。每种电路用2种方法实现：Verilog语言描述和LPM。并比较其不同。Part I 8-bit的加法器要求：1. 支持有符号的数的2的补码的形式； 2. 带溢出信号，当结果不对时，溢出为1； 代码part1.v 1 /* 2 *(C) yf.x 2010 3 * 4 *Complier :Quartus II 9.1 5 *Filename :adder_8b_reg.v 6 *Description:A 8-bit adder,top-level file.which support signed number in 2s complement. 7 *Release :06/30/2010 1.0 8 */ 9 10 module adder_8b_reg(SW, /加数A和B 11 KEY, /脉冲和复位 12 LEDR, /和 13 LEDG, /溢出 14 HEX7, /16进制显示加数A 15 HEX6, 16 HEX5, /16进制显示加数B 17 HEX4, 18 HEX1, /16进制显示和 19 HEX0 20 ); 21 22 input 15:0SW; 23 input 1:0KEY; 24 output 7:0LEDR; 25 output 8:8LEDG; 26 output 6:0HEX7,HEX6,HEX5,HEX4,HEX1,HEX0; 27 28 adder u0(.A(SW15:8), 29 .B(SW7:0), 30 .clk(KEY1), 31 .rst_n(KEY0), 32 .sum(LEDR), 33 .overflow(LEDG) 34 ); 35 36 seg7_lut u1(.oseg(HEX7), 37 .idig(SW15:12) 38 ); 39 seg7_lut u2(.oseg(HEX6), 40 .idig(SW11:8) 41 ); 42 seg7_lut u3(.oseg(HEX5), 43 .idig(SW7:4) 44 ); 45 seg7_lut u4(.oseg(HEX4), 46 .idig(SW3:0) 47 ); 48 seg7_lut u5(.oseg(HEX1), 49 .idig(LEDR7:4) 50 ); 51 seg7_lut u6(.oseg(HEX0), 52 .idig(LEDR3:0) 53 ); 54 55 endmodule 56 57 /* 58 *(C) yf.x 2010 59 * 60 *Complier :Quartus II 9.1 61 *Filename :adder.v 62 *Description:A 8-bit adder,which support signed number in 2s complement. 63 *Release :06/30/2010 1.0 64 */ 65 66 67 /=pins instruction=/ 68 / A | SW15:8 | HEX7:6 69 / B | SW7:0 | HEX5:4 70 / clk | KEY1 71 / rst_n | KEY0 72 / sum | LEDR7:0 | HEX1:0 73 / overflow | LEDG8 74 /=/ 75 module adder (A, 76 B, 77 clk, 78 rst_n, 79 sum, 80 overflow 81 ); 82 83 parameter n=8; 84 input n-1:0A,B; 85 input clk,rst_n; 86 output n-1:0sum; 87 output overflow; 88 reg overflow; 89 reg n-1:0Areg,Breg,Sreg; 90 wire n-1:0Sw; 91 wire cout,over_flow; 92 93 94 addern n_bit_adder(0,Areg,Breg,Sw,cout); 95 defparam n_bit_adder.n=8; 96 assign over_flow=coutAregn-1Bregn-1Swn-1; 97 assign sum=Sreg; 98 99 always (posedge clk or negedge rst_n)100 if(!rst_n)101 begin102 Areg=0;103 Breg=0;104 Sreg=0;105 overflow=0;106 end107 else108 begin109 Areg=A;110 Breg=B;111 Sreg=Sw;112 overflow=over_flow;113 end114 endmodule115 116 /*117 *(C) yf.x 2010 118 *119 *Complier :Quartus II 9.1120 *Filename :addern.v121 *Description:8-bit 行波进位加法器122 *Release :06/30/2010 1.0123 */124 125 module addern(carryin,X,Y,S,carryout);126 parameter n=8;127 input carryin;128 input n-1:0X,Y;129 output reg n-1:0S;130 output reg carryout;131 reg n:0C;132 integer k;133 134 always (X,Y,carryin)135 begin136 C0=carryin;137 for(k=0;kn;k=k+1)138 begin139 Sk=XkYkCk;140 Ck+1=(Xk&Yk)|(Xk&Ck)|(Yk&Ck);141 end142 carryout=Cn;143 end 144 145 146 endmodule147 148 149 图1 part1编译结果这部分要注意的就是2的补码的表示，和溢出信号的推导。可参阅Reference【1】。Part II 加、减电路要求：在part I的基础上修改，使其可做加、减运算。代码part2.v 1 /* 2 *(C) yf.x 2010 3 * 4 *Complier :Quartus II 9.1 5 *Filename :part2.v 6 *Description:Top-level file of addersubtractor circuit. 7 *Release :06/30/2010 1.0 8 */ 9 10 module part2 (SW, /加数A和B 11 KEY, /脉冲和复位 12 LEDR, /和 13 LEDG, /溢出 14 HEX7, /16进制显示加数A 15 HEX6, 16 HEX5, /16进制显示加数B 17 HEX4, 18 HEX1, /16进制显示和 19 HEX0 20 ); 21 22 input 16:0SW; 23 input 1:0KEY; 24 output 7:0LEDR; 25 output 8:8LEDG; 26 output 6:0HEX7,HEX6,HEX5,HEX4,HEX1,HEX0; 27 wire 7:0sum; 28 29 addersubtractor u0(.A(SW15:8), 30 .B(SW7:0), 31 .clk(KEY1), 32 .rst_n(KEY0), 33 .S(sum), 34 .overflow(LEDG), 35 .addsub(SW16) 36 ); 37 38 assign LEDR=sum; 39 40 seg7_lut u1(.oseg(HEX7), 41 .idig(SW15:12) 42 ); 43 seg7_lut u2(.oseg(HEX6), 44 .idig(SW11:8) 45 ); 46 seg7_lut u3(.oseg(HEX5), 47 .idig(SW7:4) 48 ); 49 seg7_lut u4(.oseg(HEX4), 50 .idig(SW3:0) 51 ); 52 seg7_lut u5(.oseg(HEX1), 53 .idig(sum7:4) 54 ); 55 seg7_lut u6(.oseg(HEX0), 56 .idig(sum3:0) 57 ); 58 59 endmodule 60 61 /* 62 *(C) yf.x 2010 63 * 64 *Complier :Quartus II 9.1 65 *Filename :addersubtractor.v 66 *Description:addersubtractor ciucuit. 67 *Release :06/30/2010 1.0 68 */ 69 70 /Top-level module 71 module addersubtractor(A, 72 B, 73 clk, 74 rst_n, 75 addsub, /0=+,1=-; 76 S, 77 overflow 78 ); 79 parameter n=8; 80 input n-1:0A,B; 81 input clk,rst_n,addsub; 82 output n-1:0S; 83 output overflow; 84 85 reg addsub_r,overflow; 86 reg n-1:0Areg,Breg,Sreg; 87 wire n-1:0G, H,M; 88 wire cout,over_flow; 89 90 /Define combinational logic circuit 91 assign H=Bregnaddsub_r,G=Areg; 92 addern u0(addsub_r,G,H,M,cout); 93 defparam u0.n=n; 94 assign over_flow=coutGn-1Hn-1Mn-1; 95 assign S=Sreg; 96 97 /Define flip-flops and registers 98 always (posedge clk or negedge rst_n) 99 if(!rst_n)100 begin 101 Areg=0;102 Breg=0;103 Sreg=0;104 overflow=0;105 addsub_r=0;106 end107 else108 begin109 Areg=A;110 Breg=B;111 Sreg=M;112 overflow=over_flow;113 addsub_r=addsub;114 end115 endmodule 图2 Part II编译结果这部分，很简单，由2的补码表示可知，减法运算变为加法，只需要在part I加一个控制信号add_sub,并将其作为cin，当其为1时，即为减法。Part III 使用lpm_add_sub实现Part I代码part3.v 1 /Top-level file 2 module part3 (SW, /加数A和B 3 KEY, /脉冲和复位 4 LEDR, /和 5 LEDG, /溢出 6 HEX7, /16进制显示加数A 7 HEX6, 8 HEX5, /16进制显示加数B 9 HEX4, 10 HEX1, /16进制显示和 11 HEX0 12 ); 13 14 input 15:0SW; 15 input 1:0KEY; 16 output 7:0LEDR; 17 output 8:8LEDG; 18 output 6:0HEX7,HEX6,HEX5,HEX4,HEX1,HEX0; 19 20 reg 7:0Areg,Breg,Sreg; 21 wire over_flow; 22 wire 7:0S,H,M; 23 24 assign LEDR=S; 25 assign LEDG=over_flow; 26 assign H=Areg,M=Breg; 27 28 lpa_add8 nbit_adder(.cin(0), 29 .dataa(H7:0), 30 .datab(M7:0), 31 .overflow(over_flow), 32 .result(S) 33 ); 34 35 always (posedge KEY1 or negedge KEY0) 36 if(!KEY0) 37 begin 38 Areg=0; 39 Breg=0; 40 Sreg=0; 41 42 end 43 else 44 begin 45 Areg=SW15:8; 46 Breg=SW7:0; 47 Sreg=S; 48 49 end 50 51 seg7_lut u1(.oseg(HEX7), 52 .idig(H7:4) 53 ); 54 seg7_lut u2(.oseg(HEX6), 55 .idig(H3:0) 56 ); 57 seg7_lut u3(.oseg(HEX5), 58 .idig(M7:4) 59 ); 60 seg7_lut u4(.oseg(HEX4), 61 .idig(M3:0) 62 ); 63 seg7_lut u5(.oseg(HEX1), 64 .idig(S7:4) 65 ); 66 seg7_lut u6(.oseg(HEX0), 67 .idig(S3:0) 68 ); 69 70 endmodule 71 72 / synopsys translate_off 73 timescale 1 ps / 1 ps 74 / synopsys translate_on 75 module lpa_add8 ( 76 cin, 77 dataa, 78 datab, 79 overflow, 80 result); 81 82 input cin; 83 input 7:0 dataa; 84 input 7:0 datab; 85 output overflow; 86 output 7:0 result; 87 88 wire sub_wire0; 89 wire 7:0 sub_wire1; 90 wire overflow = sub_wire0; 91 wire 7:0 result = sub_wire17:0; 92 93 lpm_add_sub lpm_add_sub_component ( 94 .dataa (dataa), 95 .datab (datab), 96 .cin (cin), 97 .overflow (sub_wire0), 98 .result (sub_wire1) 99 / synopsys translate_off100 ,101 .aclr (),102 .add_sub (),103 .clken (),104 .clock (),105 .cout ()106 / synopsys translate_on107 );108 defparam109 lpm_add_sub_component.lpm_direction = ADD,110 lpm_add_sub_component.lpm_hint = ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES,111 lpm_add_sub_component.lpm_representation = SIGNED,112 lpm_add_sub_component.lpm_type = LPM_ADD_SUB,113 lpm_add_sub_component.lpm_width = 8;114 115 116 endmodulePart IV 用lpm_add_sub实现Part II代码part4.v 1 module part4 (SW, /加数A和B 2 KEY, /脉冲和复位 3 LEDR, /和 4 LEDG, /溢出 5 HEX7, /16进制显示加数A 6 HEX6, 7 HEX5, /16进制显示加数B 8 HEX4, 9 HEX1, /16进制显示和 10 HEX0 11 ); 12 13 input 16:0SW; 14 input 1:0KEY; 15 output 7:0LEDR; 16 output 8:8LEDG; 17 output 6:0HEX7,HEX6,HEX5,HEX4,HEX1,HEX0; 18 wire 7:0sum; 19 reg 7:0Areg,Breg,Sreg; 20 wire over_flow,cout; 21 wire 7:0Aw,Bw; 22 23 24 assign Aw=Areg,Bw=Breg; 25 26 27 always (posedge KEY1 or negedge KEY0) 28 begin 29 if(!KEY0) 30 begin 31 Areg=0; 32 Breg=0; 33 Sreg=0; 34 end 35 else 36 begin 37 Areg=SW15:8; 38 Breg=SW7:0; 39 Sreg=sum; 40 end 41 end 42 43 44 lpm_addsub u0(.dataa(Aw), 45 .datab(Bw), 46 .cin(SW16), 47 .cout(cout), 48 .result(sum), 49 .overflow(over_flow), 50 .add_sub(SW16) 51 ); 52 53 assign LEDR=sum,LEDG=over_flow; 54 55 seg7_lut u1(.oseg(HEX7), 56 .idig(SW15:12) 57 ); 58 seg7_lut u2(.oseg(HEX6), 59 .idig(SW11:8) 60 ); 61 seg7_lut u3(.oseg(HEX5), 62 .idig(SW7:4) 63 ); 64 seg7_lut u4(.oseg(HEX4), 65 .idig(SW3:0) 66 ); 67 seg7_lut u5(.oseg(HEX1), 68 .idig(sum7:4) 69 ); 70 seg7_lut u6(.oseg(HEX0), 71 .idig(sum3:0) 72 ); 73 74 endmodule 75 76 / synopsys translate_off 77 timescale 1 ps / 1 ps 78 / synopsys translate_on 79 module lpm_addsub ( 80 add_sub, 81 cin, 82 dataa, 83 datab, 84 cout, 85 overflow, 86 result); 87 88 input add_sub; 89 input cin; 90 input 7:0 dataa; 91 input 7:0 datab; 92 output cout; 93 output overflow; 94 output 7:0 result; 95 96 wire sub_wire0; 97 wire sub_wire1; 98 wire 7:0 sub_wire2; 99 wire overflow = sub_wire0;100 wire cout = sub_wire1;101 wire 7:0 result = sub_wire27:0;102 103 lpm_add_sub lpm_add_sub_component (104 .dataa (dataa),105 .add_sub (add_sub),106 .datab (datab),107 .cin (cin),108 .overflow (sub_wire0),109 .cout (sub_wire1),110 .result (sub_wire2)111 / synopsys translate_off112 ,113 .aclr (),114 .clken (),115 .clock ()116 / synopsys translate_on117 );118 defparam119 lpm_add_sub_component.lpm_direction = UNUSED,120 lpm_add_sub_component.lpm_hint = ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES,121 lpm_add_sub_component.lpm_representation = SIGNED,122 lpm_add_sub_component.lpm_type = LPM_ADD_SUB,123 lpm_add_sub_component.lpm_width = 8;124 125 126 endmodule127 128 / =129 / CNX file r图3 Part IV时序分析Part V 4X4乘法器代码part5.v 1 /Top-level file 2 module part5(SW, /SW11:8=A,SW3:0=B 3 HEX6, /A 4 HEX4, /B 5 HEX1, /P 6 HEX0 7 ); 8 9 input 11:0SW;10 output 6:0HEX6,HEX4,HEX1,HEX0; 11 wire 7:0P; 12 13 multiplier u0(SW11:8,SW3:0,P);14 seg7_lut A(.oseg(HEX6),15 .idig(SW11:8)16 );17 seg7_lut B(.oseg(HEX4),18 .idig(SW3:0)19 );20 seg7_lut p1(.oseg(HEX1),21 .idig(P7:4)22 );23 seg7_lut p0(.oseg(HEX0),24 .idig(P3:0)25 );26 endmodule27 28 /multiplier29 module multiplier(A,B,P);30 input 3:0A,B;31 output 7:0P;32 33 wire 3:1ctop,csecond,cbottom;34 wire 5:2pp1;35 wire 6:3pp2;36 37 assign P0=A0&B0;38 39 u0 toprow_stage0(A1,A0,B1,B0,0,ctop1,P1);40 u0 toprow_stage1(A2,A1,B1,B0,ctop1,ctop2,pp12);41 u0 toprow_stage2(A3,A2,B1,B0,ctop2,ctop3,pp13);42 u0 toprow_stage3(0,A3,B1,B0,ctop3,pp15,pp14);43 u1 secondrow_stage0(pp12,A0,B2,0,csecond1,P2);44 u1 secondrow_stage1(pp13,A1,B2,csecond1,csecond2,pp23);45 u1 secondrow_stage2(pp14,A2,B2,csecond2,csecond3,pp24);46 u1 secondrow_stage3(pp15,A3,B2,csecond3,pp26,pp25);47 u1 bottomrow_stage0(pp23,A0,B3,0,cbottom1,P3);48 u1 bottomrow_stage1(pp24,A1,B3,cbottom1,cbottom2,P4);49 u1 bottomrow_stage2(pp25,A2,B3,cbottom2,cbottom3,P5);50 u1 bottomrow_stage3(pp26,A3,B3,cbottom3,P7,P6);51 52 endmodule53 54 module u0(a_k1,a_k,b1,b0,cin,cout,s);55 input a_k1,a_k,b1,b0,cin;56 output cout,s;57 wire x,y;58 59 assign x=a_k1&b0;60 assign y=a_k&b1; 61 62 fulladd FA(cin,x,y,cout,s);63 64 endmodule65 66 module u1(ppi_k1,a_k,bj,cin,cout,s);67 input ppi_k1,a_k,bj,cin;68 output cout,s;69 70 wire y;71 72 assign y=bj&a_k;73 74 fulladd FA(cin,ppi_k1,y,cout,s);75 76 endmodule77 78 module fulladd(cin,a,b,cout,s);79 input cin,a,b;80 output reg cout,s;81 82 always (cin,a,b)83 cout,s=a+b+cin;84 85 endmodule图4 part V仿真Part VI 8X8乘法器代码part6.v 1 /Top-level file 2 module part6(SW, 3 KEY, 4 HEX7, 5 HEX6, 6 HEX5, 7 HEX4, 8 HEX3, 9 HEX2, 10 HEX1, 11 HEX0 12 ); 13 14 input 15:0SW; /A,B 15 input 1:0KEY; /clk & rst_n 16 output 6:0HEX7,HEX6, /A 17 HEX5,HEX4, /B 18 HEX3,HEX2,HEX1,HEX0; /P 19 20 reg 7:0Areg,Breg; 21 reg 15:0Preg; 22 wire 7:0Aw,Bw; 23 wire 15:0Pw,P; 24 25 always (posedge KEY1 or negedge KEY0) 26 if(!KEY0) 27 begin 28 Areg=0; 29 Breg=0; 30 Pre