Quartus-II英文教程.ppt

DesigningwithQuartusII 2 Objectives CreateaNewQuartusIIProjectCompileaDesignintoanFPGALocateResultingCompilationInformationAssignDesignConstraints Timing Pin PerformTimingAnalysis ObtainResultsCreateSimulationWaveform SimulateaDesignConfigureanFPGA 3 ClassAgenda ProjectsExercise1DesignMethodologyinQuartus IIExercise2CompilationExercise3Single Multi ClockTimingAnalysisExercise4 5SimulationExercise6Programming ConfigurationExercise7or8 DesigningwithQuartusII IntroductiontoAltera AlteraDevices 5 IntellectualProperty IP SignalProcessingCommunicationsEmbeddedProcessorsNios II Devices continued MAX IIMercury DevicesACEX DevicesFLEX DevicesMAXDevices ToolsQuartus IISoftwareSOPCBuilderDSPBuilderNiosIIIDE DevicesStratix II Cyclone IIStratixGXStratixCyclone TheProgrammableSolutionsCompany 6 StructuredASICHardCopy II HardCopyStratixHigh MediumDensityFPGAsStratix II Stratix APEX II APEX20K FLEX 10KLow CostFPGAsCyclone II CycloneFPGAswithClockDataRecoveryStratixGX Mercury CPLDsMAX II MAX7000 MAX3000EmbeddedProcessorSolutionsNios II Excalibur ConfigurationDevicesSerial EPCS Enhanced EPC ProgrammableLogicFamilies 7 Software DevelopmentTools QuartusIIAllStratix Cyclone HardcopyDevicesAPEXII APEX20K E C Excalibur MercuryDevicesFLEX10K A E ACEX1K FLEX6000DevicesMAXII MAX7000S AE B MAX3000ADevicesQuartusIIWebEditionFreeVersionNotAllFeatures DevicesIncludedSforFeatureComparisonMAX PLUS IIAllFLEX ACEX MAXDevices DesigningwithQuartusII QuartusIIDevelopmentSystemFeatureOverview QuartusIIDevelopmentSystem Fully IntegratedDesignToolMultipleDesignEntryMethodsLogicSynthesisPlace RouteSimulationTiming PowerAnalysisDeviceProgramming 10 MoreFeatures MegaWizard SOPCBuilderDesignToolsIncrementalDesignFlowLogicLock OptimizationToolPowerPlayPowerAnalyzerToolNativeLink 3rd PartyEDAToolIntegrationDebugToolsSignalTap IISignalProbe In SystemMemoryContentEditorWindows Solaris HPUX LinuxSupportNode Locked NetworkLicensingOptions 11 QuartusIIOperatingEnvironment ProjectNavigator StatusWindow MessageWindow 12 MainToolbar Modes ToResetViews Tools Toolbars ResetAll RestartQuartusII Window newfilebuttons CompilerReport Floorplan ExecutionControls Dynamicmenus DesigningwithQuartusII DesignMethodology 14 PLDDesignFlow Synthesis TranslateDesignintoDeviceSpecificPrimitives OptimizationtoMeetRequiredArea PerformanceConstraints Precision Synplify QuartusII DesignSpecification Place Route MapPrimitivestoSpecificLocationsinsideTargetTechnologywithReferencetoArea PerformanceConstraints SpecifyRoutingResourcestoBeUsed DesignEntry RTLCoding BehavioralorStructuralDescriptionofDesign RTLSimulation FunctionalSimulation Modelsim QuartusII VerifyLogicModel DataFlow NoTimingDelays LE M512 M4K I O 15 PLDDesignFlow TimingAnalysis VerifyPerformanceSpecificationsWereMet StaticTimingAnalysis GateLevelSimulation TimingSimulation VerifyDesignWillWorkinTargetTechnology PCBoardSimulation Test SimulateBoardDesign Program TestDeviceonBoard UseSignalTapIIforDebugging tclk DesigningwithQuartusII QuartusIIProjects 17 QuartusIIProjects DescriptionCollectionofRelatedDesignFiles LibrariesMustHaveaDesignatedTop LevelEntityTargetaSingleDeviceStoreSettingsinQuartusSettingsFile QSF CreateNewProjectswithNewProjectWizardCanBeCreatedUsingTclScripts 18 NewProjectWizard NameofProjectCanBeAnyName RecommendUsingTop LevelFileName SelectWorkingDirectory Top levelEntityDoesNotNeedtoBetheSameNameasTop LevelFileName FileMenu CreateaNewProjectBasedonanExistingProject Settings 19 AddDesignFilesGraphic BDF GDF AHDLVHDLVerilogEDIFNotes FilesinprojectdirectorydonotneedtobeaddedAddtoplevelfileiffilename entitynamearenotthesame AddUserLibraryPathnamesUserLibrariesMegaCore AMPPSMLibrariesPre CompiledVHDLPackages AddFiles 20 ChooseSpecificPartNumberfromListorLetQuartusIIChooseSmallestFastestDeviceBasedonFilterCriteria ChooseDeviceFamily DeviceSelection 21 ChooseEDAToolsAddorChangeSettingsLater EDAToolSettings 22 ReviewResults ClickonFinish Done 23 MAX PLUSIItoQuartusII ConvertMAX PLUSIIProjectsintoQuartusIIProjectsAssignmentsAutomaticallyTranslated 24 OpeningaProject File OpenProject Double Clickingthe QPFFileWillAutoLaunchQuartusII OR OR SelectfromMostRecentProjectsList 25 DisplaysProjectHierarchyafterProjectIsAnalyzedUsesSetTop LevelEntitySetIncrementalDesignPartitionMakeEntity LevelAssignmentsLocateinDesignFileorViewers FloorplansViewResourceUsage ProjectNavigator HierarchyTab Select Right Click 26 Files DesignUnitsTabs FilesTabShowsFilesExplicitlyAddedtoProjectUsesOpenFilesRemoveFilesfromProjectSetNewTop LevelEntitySpecifyVHDLLibrarySelectFile SpecificSynthesisToolDesignUnitsTabDisplaysDesignUnit TypeVHDLEntityVHDLArchitectureVerilogModuleAHDLSubdesignBlockDiagramFilenameDisplaysFilewhichInstantiatesDesignUnit 27 ProjectFiles QuartusProjectFile QPF QuartusIIVersionTimeStampActiveRevisionQuartusDefaultFile QDF ProjectDefaultsName assignment defaults qdfLocalorBinDirectoryLocalReadFirst QUARTUS VERSION 5 0 DATE 15 37 58April16 2005 ActiveRevisionsPROJECT REVISION filtref PROJECT REVISION filtref new COMPILE FILTER QPF 28 ProjectManagement ProjectArchive RestoreCreatesCompressedArchiveFile QAR CreatesArchiveActivityLog QARLOG ProjectCopyCopies SaveDuplicateofProjectinNewDirectoryProjectFile QPF DesignFilesSettingsFiles ArchiveProject CopyProject 29 PleasegotoExercise1intheExerciseManual 30 CreatedaNewProjectusingtheNewProjectWizard ExerciseSummary 31 ProjectsEntrySummary ProjectsNecessaryforDesignProcessingUseProjectWizardtoCreateNewProjectsUseProjectNavigatortoStudyFile EntityRelationshipswithinProject DesigningwithQuartusII DesignEntry 33 DesignEntryMethods QuartusIITextEditorAHDLVHDLVerilogSchematicEditorBlockDiagramFileGraphicDesignFileMemoryEditorHEXMIF3rd PartyEDAToolsEDIFHDLVQMMixing MatchingDesignFilesAllowed 34 TextDesignEntry AvailableFeaturesLineNumberingintheHDLTextFilesPreviewofHDLTemplatesSyntaxColoringWhenEditingaTextFile anAsterisk AppearsNexttotheFilenameAsteriskDisappearsafterSavingtheFileEnterTextDescriptionAHDL tdf VHDL vhd vhdl Verilog v vlg verilog vh 35 Verilog VHDL VHDL VHSICHardwareDescriptionLanguage1987 1993IEEE1074StandardsSupportedVerilog 1995 2001IEEE1364StandardHDLCreateinQuartusIIoranyStandardTextEditorUseQuartusIIIntegratedSynthesistoSynthesizeViewSupportedCommandsinOn LineHelp LearnmoreaboutHDLinAlteraHDLCustomerTrainingClasses 36 AHDL AlteraHardwareDescriptionLanguageHigh LevelHardwareBehaviorDescriptionLanguageUsedinAlteraMegafunctionsUsesBooleanEquations ArithmeticOperators TruthTables ConditionalStatements etc CreateinQuartusIIoranyStandardTextEditor 37 HDLTemplates MenuBar Edit InsertTemplate orClickontheShortcutButton SelectLanguage SelectTemplateSection PreviewWindowDisplaySection 38 SchematicDesignEntry Full FeaturedSchematicDesignCapabilitySchematicDesignCreationDrawSchematicsUsingLibraryFunctions Blocks Gates Flip flops Pins OtherPrimitivesAlteraMegafunctions LPMsCreateSymbolsforVerilog VHDL orAHDLDesignFilesConnectAllBlocksUsingWires BussesSchematicEditorUsesCreateSimpleTestDesignstoUnderstandtheFunctionalityofanAlteraMegafunctionPLL LVDSI O Memory Etc CreateTop LevelSchematicforEasyViewing Connection 39 UsetheQuickLinkorFile New SchematicFile FileExtensionIs BDF CreateSchematic 40 OpentheSymbolWindow UsetheToolbarorDoubleClickSchematicBackground LocalSymbolsCreatedfromMegaWizardorDesignFiles LibrarySymbols InsertSymbols 41 DrawWires Buses orConduit ConnectWires Buses 42 Double ClickonPinNametoChange HitEntertoAdvancetoNextPin ChangeNames Properties Right ClickonanyBlocktoChangeProperties Ex InstanceName 43 File Create Update CreateSymbol Note SchematicCanBeConvertedtoaSymbol UsedinotherSchematics SymbolCreatedinProjectDirectory CreateSymbols 44 Megafunctions Pre MadeDesignBlocksEx Multiply Accumulate PLL Double DataRateBenefitsFree InstalledwithQuartusIIAccelerateDesignEntryPre OptimizedforAlteraArchitectureAddFlexibilityTwoTypesAltera SpecificMegafunctions Beginwith ALT LibraryofParamerterizedModules LPMs IndustryStandardLogicFunctionsSeewww edif org lpmwebformoreinfo 45 MegaWizardPlug InManager EasesImplementationofMegafunctions IP Tools MegaWizardPlug InManager 46 MegaWizardExamples Multiply Add PLL Double DataRate LocateDocumentationinQuartusIIHelportheWeb 47 MegaWizardOutputFileSelection DefaultHDLWrapperFileSelectableHDLInstantiationTemplateVHDLComponentDeclaration CMP QuartusIISymbol BSF VerilogBlackBox 48 BehavioralWaveforms HTMLfileGeneratedbyMegaWizardDescriptionofMegafunctionFunctionalityReviewsSelectedParametersDescribesRead WriteOperationsSupportedMegafunctionsSubsetofMemorySubsetofArithmetic 49 ExampleWaveform 50 MemoryEditor CreateorEditMemoryInitializationFilesinIntelHex HEX orAltera Specific MIF FormatDesignEntryUsetoInitializeYourMemoryBlock Ex RAM ROM duringPower UpSimulationUsetoInitializeMemoryBlocksbeforeSimulationorafterBreakpoints 51 File New OtherFilestab 1 HEXformatorMIFformat CreateMemoryInitializationFile 2 SelectMemorySize 3 MemorySpace 52 ChangeOptions ViewOptionsofMemoryEditorView SelectfromAvailableOptions 53 SelecttheWord TypeinaValueORSelecttheWord RightClicktoSelectanOptionfromthePop UpMenuORCopy PastefromaSpreadsheetintoaMemoryFile EditContents EditContentsoftheMemoryFileSavetheMemoryFileas HEXor MIFFile 54 MemorySizeWizard NeedtoEditSizeofMemoryFile UsetheMemorySizeWizard EditMenu EditWordSizeEditNumberofWordsSpecifyHowtoHandleWordSizeChangeIncreasingWordSizePadWordsCombineWordsDecreasingWordSizeTruncateWordsfromLeftTruncateWordsfromRight 55 UsingMemoryFileinDesign SpecifyMIForHEXfileinMegaWizardInterface 56 EDAInterfacesIntroduction InterfacewithIndustry StandardEDAToolsthatGenerateaNetlistFileEDIF200VHDL 87or 93VerilogNativeLinkInterfaceProvidesSeamlessIntegrationwith3rd partyEDASoftwareToolsToolsPassInformation CommandsinBackgroundDesignersCanCompleteEntireDesigninOneTool 57 ComprisedofTwoComponentsExternalFilesWYSIWYG WhatYouSeeIsWhatYouGet ATOMNetlistFiles EDIF Verilog VHDL CrossReferenceFiles Ex XRF TimingFiles Ex SDO ApplicationProgrammingInterface API Pre DefinedInterfaceofCommands Functions EDAPartners API NativeLink 58 SetofDesignPrimitivesthatSupportWYSIWYGCompilationProvideDirectControlofHowaDesignIsTechnology MappedtoaSpecificTargetDeviceAllowSynthesisVendorstoProvideanOptimalRealizationofaDesignforEachArchitecture Synplify vqm WYSIWYGATOMPrimitives 59 WYSIWYGCompilationFlow EDASynthesisPartner EDFVQM DesignInputFileswithWYSIWYGPrimitives Synthesis LogicSynthesis NetlistExtraction DatabaseBuilder Place Route Note LogicOptionsinQuartusIIthatcontrolsynthesiscannolongerbeused 60 ThreeEDADesignFlows QuartusIIDrivenFlowUserLaunchesotherEDAToolsfromQuartusIIintheBackgroundMessagesAppearinQuartusIIMessageWindowVendorDrivenFlowUserRunsQuartusIIintheBackgroundfromthe3rd PartyEDAToolFileBasedFlowEachToolRanSeparatelyFilesAreManuallyTransferredbetweenTools 61 QuartusIIDrivenorFile BasedFlow Assignments EDAToolSettings Checkthe Run ButtontoLaunchtheEDAToolintheBackgroundLeaveUncheckedforFileBasedFlow 62 EDADrivenFlow RunQuartusIIFitterintheBackgroundbySelectingRunBackgroundCompileorLaunchQuartusII 63 VerificationToolsModelSim ModelSim AlteraCadenceVerilog XLCadenceNC VerilogCadenceNC VHDLInnovedaBLASTPrimeTime Synopsys VCS VSSMentorGraphics TauSynopsysScirocco SynthesisToolsLeonardoSpectrum PrecisionDesignCompiler FPGAFPGACompilerIIFPGAExpressSynplifySynplifyProAmplify ThirdPartyToolSupport 64 PleasegotoExercise2intheExerciseManual 65 CreatedaSchematicDesignGeneratedLogicUsingMegaWizardConvertedHDLFiletoSymbolforInclusioninSchematicPerformedAnalysis ElaborationtoChecktheFile ExerciseSummary 66 DesignEntrySummary MultipleDesignEntryMethodsText Verilog VHDL AHDL ThirdPartyNetlist VQM EDF SchematicMemoryEditorMegaWizardEDAToolFlows DesigningwithQuartusII QuartusIICompilation 68 QuartusIICompilation SynthesisFittingGeneratingOutputTimingAnalysisOutputNetlistSimulationOutputNetlistsProgramming ConfigurationOutputFiles 69 StartCompilationPerformFullCompilationStartAnalysis ElaborationCheckSyntax BuildDatabaseOnlyStartAnalysis SynthesisSynthesizeCodeEstimateTimingStartFitterStartAssemblerStartTimingAnalysisStartI OAssignmentAnalysisStartDesignAssistant ProcessingOptions ProcessingToolbar 70 CompilationDesignFlows StandardFlowDesignCompiledasaWholeGlobalOptimizationsPerformedIncrementalFlowUserControlsHow WhenPre SelectedPartsofDesignAreCompiledBenefitsDecreaseCompilationTimeMaintain ImproveCompilationResultsTwoTypesIncrementalSynthesisIncrementalFitting 71 B inst2 IncrementalCompilationConcept B OnlySpecifiedPortionsofLogicthatHaveChangedAreRe SynthesizedorRe Fitted ChoosetoReusePost SynthesisorPost FitNetlist 72 Ex TypicalUserFlow MarkPartitionsUsingProjectNavigatorRunAnalysis ElaborationorAnalysis SynthesisChooseNetlistTypeforEachPartitionMakeDesignChangesforAnyPartitionPerformIncrementalCompilation Right ClickonHierarchicalLevelinProjectNavigator Note Formoredetailsonusingincrementalcompilation pleaseattendthecourse AcceleratingDesignCyclesusingQuartusII orwatchtheweb recording IncrementalDesigninQuartusII 73 StatusBarsScrolltoIndicateProgressMessageWindowDisplaysInformational Warning ErrorMessages Status MessageWindows 74 ContainsAllProcessingInformationResourceUsageTimingAnalysisPin OutFileMessages CompilationReport 75 SeveralSectionsDetailtheResourceUsage ResourceUsage 76 TimingClosureFloorplan EditableViewofTargetTechnologyUsedto ViewPlacementViewConnectivityMakePlacementAssignments AssignmentsMenu 77 Synthesis FittingControl ControlledUsingTwoMethodsSettingsProject WideSwitchesAssignments i e LogicOptions Constraints IndividualEntity NodeControlsAccessedUsingAssignmentsMenuStoredinQSFFile 78 QuartusSettingsFile QSF StoresAllSettings AssignmentsUsesTclSyntax OrganizedbyAssignmentType 79 Settings ExamplesDeviceSelectionSynthesisOptimizationFitterSettingsPhysicalSynthesisLocatedinSettingsDialogBox AssignmentsMenu 80 SettingsDialogBox ChangeSettingsTop LevelEntityTargetDeviceAdd RemoveFilesLibrariesVHDL 87 93 Verilog 95 01 EDAToolSettingsTimingSettingsCompilerSettingsSimulatorSettings 81 SmartCompilationSkipsEntireCompilerModuleswhenNotRequired i e Elaboration Synthesis etc SavesCompilerTimeUsesMoreDiskSpacePreserveFewerNodeNamesDisableforVHDL VerilogSynthesisGenerateVersion CompatibleDatabaseEnableIncrementalCompilation CompilationProcess 82 Version CompatibleDatabase RecommendedExportsaDatabasethatCanBeOpenedDirectlyinanotherVersionofQuartusIIImportDatabaseintoNewVersionTwoMethodstoCreateSettingsDialogBoxProjectMenu AnalyzePreviouslyCompiledProjectsUsingUpdatedTimingModels 83 GlobalOptimizationGoal Default SelectSpeedvs AreaorBalancedLogicReplacementReplaceLogicwithEquivalentMegafunctionStateMachineProcessingAuto One HotorMinimalBit SynthesisOptions 84 SynthesisNetlistOptimizations FurtherOptimizeNetlistsduringSynthesisTypesWYSIWYGPrimitiveResynthesisGate LevelRegisterRetiming Created ModifiedNodesNotedinCompilationReport 85 WYSIWYGPrimitiveResynthesis Unmaps3rd PartyAtomNetlistBacktoGates thenRemapstoAlteraPrimitivesUnavailablewhenUsingIntegratedSynthesisConsiderationsNodeNamesMayChange3rd PartySynthesisAttributesMayBeLostPreserve KeepSomeRegistersMayBeSynthesizedAway 86 Gate LevelRegisterRetiming MovesRegistersacrossCombinatorialLogictoBalanceTimingTradesbetweenCritical Non CriticalPathsMakesChangesatGateLevel 87 TimingDrivenCompilationDiscussedLaterCompilationSpeed FitterEffortStandardFitHighestEffortFastFitFasterCompilebutPossiblyLesserDesignPerformanceAutoFitCompileStopsafterMeetingTimingConservesCPUTimeDefaultforNewDesignsOneFittingAttempt FitterSettings 88 PhysicalSynthesis Re SynthesisBasedonFitterOutputMakesIncrementalChangesthatImproveResultsforaGivenPlacementCompensatesforRoutingDelaysfromFitterTypesCombinationalLogicRegistersRegisterDuplicationRegisterRetimingEffortTradesPerformancevsCompileTimeNormal ExtraorFast Created ModifiedNodesNotedinCompilationReport 89 CombinationalLogic SwapsLook UpTable LUT PortswithinLEstoReduceCriticalPathLEsAllowsLUTDuplicationtoEnableFurtherOptimizationsontheCriticalPath 90 RegisterDuplication HighFan OutRegisterIsDuplicated PlacedtoReduceDelayCombinationalLogicMayAlsoBeDuplicated 91 Assignments AssignmentEditorExampleAssignmentsI OAssignments AnalysisPerformAnalysis ElaborationbeforeObtainingHierarchy NodeInformation 92 AssignmentEditor AE ProvidesSpreadsheetAssignmentEntry DisplayCanCopy PastefromClipboard SortonColumns Enable DisableIndividualAssignments 93 InvoketheAssignmentEditorbyHighlightinganEntityintheHierarchyView Right Clicking OpeningAssignmentEditor AssignmentsMenu 94 OpeningAssignmentEditor cont LocatetoAssignmentEditorfromMessageWindow TimingReport etc 95 UsingAssignmentEditor SelectAssignmentfromDrop DownMenu SetValue Double ClickCellstoEditorTypeNameDirectly LaunchesNodeFinder 96 EditingMultipleAssignments UseEditBar EditingMultipleI OStandardsatOnce 97 SearchbyNameUsingWildcards or ListofNodesinSelectedEntity LowerLevelsofHierarchy UseFiltertoSelecttheNodestoBeDisplayed SelectNodesonLeft UseArrowstoMovetotheRight NodeFinder LocateNodesinaCertainLevelofHierarchy StartDisplaysNodesMeetingSearchCriteria 98 AEDynamicChecking ValidityofConstraintCheckedduringEntryColor CodedtoDisplayStatusGrey DisabledBlack AppliedYellow AssignmentWarning DarkRed IncompleteBrightRed Error IllegalValueGreen EnterNewAssignment 99 AssignmentEditorFeatures CategoryBarSelectsCategoryofAssignmentstoViewEx PinAssignments TimingAssignmentsEachCanBeCustomizedNodeFilterBarFiltersConstraintsDisplayedBasedonNodeNameInformationBarDisplaysDescriptionofSelectedCellorAssignment 100 AETclCommands EquivalentTclCommandsAreDisplayedasAssignmentsAreEnteredManuallyCopytoCreateTclScriptsExportCommand FileMenu WritesAllAssignmentstoaTclFile MessageWindow 101 ExportCSVFileAssignments Excel ExporttoCSVFile FileMenu ImportDataintoExcel 102 ExampleAssignments OptimizationTechniquePCII OOutputPinLoad 103 OPTIMIZATIONTECHNIQUE SelectsSynthesisOptimizationGoalSpeedBalanced Default AreaAppliesOnlytoHierarchicalEntitiesEffectsSynthesis LogicMappingOnlyAppliestoQuartusIIIntegratedSynthesis 104 PCII O TurnsonPCICompatibilityforPinsIgnoredIfAppliedtoAnythingotherthan