并行乘法器-南京理工大学紫金学院vhdl实验报告-eda

EDA 技术与应用 实验报告 实验名称 并行乘法器 姓 名 学 号 班 级 通信 时 间 2013 南京理工大学紫金学院电光系南京理工大学紫金学院电光系 一 实验目的 1 学习包集和元件例化语句的使用 2 学习 FLU 全加器单元 电路的设计 3 学习并行乘法电路的设计 二 实验原理 并行乘法器的电路原理图如下图所示 主要由全加器和与门构成 并行乘法器原理图 三 实验内容 1 and 2 library ieee use ieee std logic 1164 all entity and 2 is port a b in std logic y out std logic end and 2 architecture and 2 of and 2 is begin y a and b end and 2 2 fau library ieee use ieee std logic 1164 all entity fau is port a b cin in std logic s cout out std logic end fau architecture fau of fau is begin s a xor b xor cin cout a and b or a and cin or b and cin end fau 3 top row library ieee use ieee std logic 1164 all use work my components all entity top row is port a in std logic b in std logic vector 3 downto 0 sout cout out std logic vector 2 downto 0 p out std logic end top row architecture structural of top row is begin U1 component and 2 port map a b 3 sout 2 U2 component and 2 port map a b 2 sout 1 U3 component and 2 port map a b 1 sout 0 U4 component and 2 port map a b 0 p cout 2 0 cout 1 0 cout 0 0 end structural 4 mid row library ieee use ieee std logic 1164 all use work my components all entity mid row is port a in std logic b in std logic vector 3 downto 0 sin cin in std logic vector 2 downto 0 sout cout out std logic vector 2 downto 0 p out std logic end mid row architecture structural of mid row is signal and out std logic vector 2 downto 0 begin U1 component and 2 port map a b 3 sout 2 U2 component and 2 port map a b 2 and out 2 U3 component and 2 port map a b 1 and out 1 U4 component and 2 port map a b 0 and out 0 U5 component fau port map sin 2 cin 2 and out 2 sout 1 cout 2 U6 component fau port map sin 1 cin 1 and out 1 sout 0 cout 1 U7 component fau port map sin 0 cin 0 and out 0 p cout 0 end structural 5 lower row library ieee use ieee std logic 1164 all use work my components all entity lower row is port sin cin in std logic vector 2 downto 0 p out std logic vector 3 downto 0 end lower row architecture structural of lower row is signal local std logic vector 2 downto 0 begin local 0 1100 0111 then hun 0110 0011 then hun 0001 temp p 0110 0100 else hun 0101 1001 then ten 0100 1111 then ten 0100 0101 then ten 0011 1011 then ten 0011 0001 then ten 0010 0111 then ten 0001 1101 then ten 0001 0011 then ten 0000 1001 then ten 0001 temp temp 0000