硬件电子琴及硬件乐曲演奏电路

FPGAFPGA 嵌入式系统设计专题实践嵌入式系统设计专题实践 结课论文结课论文 题目 硬件电子琴及硬件乐曲演奏电路题目 硬件电子琴及硬件乐曲演奏电路 专业 电子信息科学与技术 一 设计题目设计题目 硬件电子琴及硬件乐曲演奏电路 二 设计目标二 设计目标 1 学习利用蜂鸣器和按键设计硬件电子琴 2 利用硬件电子琴原理设计硬件演奏电路 3 掌握 VHDL 编程语言 了解实际设计中的优化方案 三 设计原理三 设计原理 音乐演奏的原理是 由于组成乐曲的每个音符的频率值 音调 及其持续时间 音长 是 乐曲演奏的两个基本数据 因此需要控制输出到扬声器的激励信号的频率高低和该频率信 号持续的时间 四 设计内容四 设计内容 1 硬件电子琴 1 原理图 2 分频器程序 filename clk div3 vhd description LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL USE IEEE STD LOGIC ARITH ALL USE IEEE STD LOGIC UNSIGNED ALL ENTITY Clk Div3 IS PORT clk in IN STD LOGIC clk out OUT STD LOGIC END ARCHITECTURE myArchitecture OF Clk Div3 is SIGNAL cnt1 cnt2 integer range 0 to 2 SIGNAL clk1 clk2 STD LOGIC BEGIN PROCESS clk in BEGIN IF rising edge clk in THEN IF cnt1 2 THEN cnt1 cnt1 1 ELSE cnt1 0 END IF IF cnt1 1 THEN clk1 1 ELSE clk1 0 END IF END IF END PROCESS PROCESS clk in BEGIN IF falling edge clk in THEN IF cnt2 2 THEN cnt2 cnt2 1 ELSE cnt2 0 END IF IF cnt2 1 then clk2 1 ELSE clk2 0 END IF END IF END PROCESS clk out clk1 OR clk2 END 3 七个中音主程序 module beepx clk key beep led ledbt 模块名称 beep input clk 系统时钟 12MHz input 7 0 key 按键输入 output beep 蜂鸣器输出端 output 7 0 led output 7 0 ledbt LED 输出 reg beep r 寄存器 reg 15 0 count count end reg 7 0 key r reg 7 0 led bt always posedge clk begin count count 1 b1 计数器加 1 if count count end 计数器清零 beep r beep r 取反输出信号 end end always key begin key r key 取键值 case key r 8 b11111110 begin count end 16 h2CCA key r 8 b11111001 led bt 8 b11111110 end 中音 1 的分频系数值 8 b11111101 begin count end 16 h27E8 key r 8 b10100100 led bt 8 b11111110 end 中音 2 的分频系数值 8 b11111011 begin count end 16 h238D key r 8 b10110000 led bt 8 b11111110 end 中音 3 的分频系数值 8 b11110111 begin count end 16 h218E key r 8 b10011001 led bt 8 b11111110 end 中音 4 的分频系数值 8 b11101111 begin count end 16 h1DE5 key r 8 b10010010 led bt 8 b11111110 end 中音 5 的分频系数值 8 b11011111 begin count end 16 h1AA2 key r 8 b10000010 led bt 8 b11111110 end 中音 6 的分频系数值 8 b10111111 begin count end 16 h17BA key r 8 b11111000 led bt 8 b11111110 end 中音 7 的分频系数值 8 b01111110 begin count end 16 h166B key r 8 b11111001 led bt 8 b11111110 end 高音 1 的分频系数值 8 b01111101 begin count end 16 h13F4 key r 8 b10100100 led bt 8 b11111110 end 高音 2 的分频系数值 8 b01111011 begin count end 16 h11C7 key r 8 b10110000 led bt 8 b11111110 end 高音 3 的分频系数值 8 b01110111 begin count end 16 h10C7 key r 8 b10011001 led bt 8 b11111110 end 高音 4 的分频系数值 8 b01101111 begin count end 16 h0EF3 key r 8 b10010010 led bt 8 b11111110 end 高音 5 的分频系数值 8 b01011111 begin count end 16 h0D51 key r 8 b10000010 led bt 8 b11111110 end 高音 6 的分频系数值 8 b00111111 begin count end 16 h0BDD key r 8 b11111000 led bt 8 b11111110 end 高音 7 的分频系数值 default count end 16 hffff endcase end assign beep beep r 输出音乐 assign led key r 输出按键状态 assign ledbt led bt endmodule 2 硬件乐曲演奏电路 1 内存分配图 2 主程序 library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC ARITH ALL use IEEE STD LOGIC UNSIGNED ALL ENTITY buzzer IS PORT ch IN std logic 键盘与歌曲播放选择 cho IN std logic 歌曲切换 key data IN std logic vector 2 DOWNTO 0 电子琴组合键盘输入 clk IN std logic 系统时钟 out bit OUT std logic 输出给蜂鸣器 END buzzer ARCHITECTURE arch OF buzzer IS COMPONENT liangzhu PORT address in std logic vector 7 downto 0 clock in std logic q out std logic vector 15 downto 0 END COMPONENT signal sta1 std logic vector 7 downto 0 signal sta integer range 0 to 147 signal count std logic vector 15 DOWNTO 0 signal count end std logic vector 15 DOWNTO 0 signal count1 std logic vector 23 DOWNTO 0 signal out bit temp std logic signal key temp std logic vector 2 DOWNTO 0 signal count end temp std logic vector 15 DOWNTO 0 signal choice std logic 音调分频数 CONSTANT suo0 std logic vector 15 DOWNTO 0 1110111100101000 61224 CONSTANT la0 std logic vector 15 DOWNTO 0 1101010100010001 54545 CONSTANT xi0 std logic vector 15 DOWNTO 0 1011110111010001 48593 CONSTANT duo std logic vector 15 DOWNTO 0 1011001100100111 45863 CONSTANT lai std logic vector 15 DOWNTO 0 1001111110100000 40864 CONSTANT me std logic vector 15 DOWNTO 0 1000111000110010 36402 CONSTANT fa std logic vector 15 DOWNTO 0 1000011000110111 34359 CONSTANT suo std logic vector 15 DOWNTO 0 0111011110010100 30612 CONSTANT la std logic vector 15 DOWNTO 0 0110101010001001 27273 CONSTANT xi std logic vector 15 DOWNTO 0 0101111011101000 24296 CONSTANT duo1 std logic vector 15 DOWNTO 0 0101100110101100 22956 CONSTANT lai1 std logic vector 15 DOWNTO 0 0100111111001001 20425 CONSTANT me1 std logic vector 15 DOWNTO 0 0100011100100001 18209 CONSTANT fa1 std logic vector 15 DOWNTO 0 0100001100011011 17179 CONSTANT suo1 std logic vector 15 DOWNTO 0 0011101111001010 15306 CONSTANT la1 std logic vector 15 DOWNTO 0 0011010101000100 13636 CONSTANT xi1 std logic vector 15 DOWNTO 0 0010111101110111 12151 CONSTANT duo2 std logic vector 15 DOWNTO 0 0010101001100011 10851 CONSTANT t std logic vector 23 DOWNTO 0 101101110001101100000000 BEGIN out bit out bit temp key temp key data PROCESS cho 歌曲间切换 BEGIN IF cho EVENT AND cho 1 THEN choice NOT choice END IF END PROCESS PROCESS clk 分频后的音调输出控制 BEGIN IF clk EVENT AND clk 1 THEN count count 1 IF count count end THEN count x 0000 out bit tempsta1 q count end temp clock clk 与 liangzhu vhd 的接口 PROCESS clk ch choice cho 音调单位时长和曲谱依次播放 sta 自加 控制 BEGIN IF ch 1 THEN 键盘与歌曲播放切换 IF clk EVENT AND clk 1 THEN IF count1 t THEN count1 count1 1 ELSE count1 x 000000 IF choice 1 THEN sta 0 IF sta1 10001010 THEN sta1 00000000 ELSE sta1 sta1 1 count end count end temp 梁祝 曲谱信息赋给 count end END IF ELSE sta1 00000000 IF sta 147 THEN sta 0 ELSE stacount endcount endcount endcount endcount endcount endcount endcount endcount endcount endcount endcount endcount endcount endcount endcount endcount endcount endcount endcount endcount endcount endcount endcount