外文翻译-ICL7135 4 二分之一 Digit, BCD Output, AD Converter

外文资料原文ICL713541/2Digit,BCDOutput,A/DConverterTheIntersilICL7135precisionA/Dconverter,withitsmultiplexedBCDoutputanddigitdrivers,combinesdual-slopeconversionreliabilitywith+1in20,000countaccuracyandisideallysuitedforthevisualdisplayDVM/DPMmarket.The2.0000Vfullscalecapability,auto-zero,andauto-polarityarecombinedwithtrueratiometricoperation,almostidealdifferentiallinearityandtruedifferentialinput.AllnecessaryactivedevicesarecontainedonasingleCMOSlC,withtheexceptionofdisplaydrivers,reference,andaclock.TheICL7135bringstogetheranunprecedentedcombinationofhighaccuracy,versatility,andtrueeconomy.Itfeaturesauto-zerotolessthan10V,zerodriftoflessthan1V/,inputbiascurrentof10pA(Max),androllovererroroflessthanonecount.TheversatilityofmultiplexedBCDoutputsisincreasedbytheadditionofseveralpinswhichallowittooperateinmoresophisticatedsystems.TheseincludeSTROBE,OVERRANGE,UNDERRANGE,RUN/HOLDandBUSYlines,makingitpossibletointerfacethecircuittoamicroprocessororUART.Features*AccuracyGuaranteedto+1CountOverEntire20000Counts(2.0000VFullScale)*GuaranteedZeroReadingfor0VInput*1pATypicalInputLeakageCurrent*TrueDifferentialInput*TruePolarityatZeroCountforPreciseNullDetection*SingleReferenceVoltageRequired*OverrangeandUnderrangeSignalsAvailableforAuto-RangeCapability*AllOutputsTTLCompatible*BlinkingOutputsGivesVisualIndicationofOverrange*SixAuxiliaryInputs/OutputsareAvailableforInterfacingtoUARTs,Microprocessors,orOtherCircuitry*MultiplexedBCDOutputs*Pb-FreeAvailable(RoHSCompliant)DetailedDescriptionAnalogSectionEachmeasurementcycleisdividedintofourphases.Theyare(1)auto-zero(AZ),(2)signal-integrate(INT),(3)de-integrate(DE)and(4)zero-integrator(Zl).Auto-ZeroPhaseDuringauto-zero,threethingshappen.First,inputhighandlowaredisconnectedfromthepinsandinternallyshortedtoanalogCOMMON.Second,thereferencecapacitorischargedtothereferencevoltage.Third,afeedbackloopisclosedaroundthesystemtochargetheauto-zerocapacitorCAZtocompensateforoffsetvoltagesinthebufferamplifier,integrator,andcomparator.Sincethecomparatorisincludedintheloop,theAZaccuracyislimitedonlybythenoiseofthesystem.Inanycase,theoffsetreferredtotheinputislessthan10V.SignalIntegratePhaseDuringsignalintegrate,theauto-zeroloopisopened,theinternalshortisremoved,andtheinternalinputhighandlowareconnectedtotheexternalpins.TheconverterthenintegratesthedifferentialvoltagebetweenINHIandINLOforafixedtime.Thisdifferentialvoltagecanbewithinawidecommonmoderange;withinonevoltofeithersupply.If,ontheotherhand,theinputsignalhasnoreturnwithrespecttotheconverterpowersupply,INLOcanbetiedtoanalogCOMMONtoestablishthecorrectcommon-modevoltage.Attheendofthisphase,thepolarityoftheintegratedsignalislatchedintothepolarityF/F.De-IntegratePhaseThethirdphaseisde-integrateorreferenceintegrate.InputlowisinternallyconnectedtoanalogCOMMONandinputhighisconnectedacrossthepreviouslychargedreferencecapacitor.Circuitrywithinthechipensuresthatthecapacitorwillbeconnectedwiththecorrectpolaritytocausetheintegratoroutputtoreturntozero.Thetimerequiredfortheout-puttoreturntozeroisproportionaltotheinputsignal.Specificallythedigitalreadingdisplayed.ZeroIntegratorPhaseThefinalphaseiszerointegrator.First,inputlowisshortedtoanalogCOMMON.Second,afeedbackloopisclosedaroundthesystemtoinputhightocausetheintegratoroutputtoreturntozero.Undernormalcondition,thisphaselastsfrom100to200clockpulses,butafteranoverrangeconversion,itisextendedto6200clockpulses.DifferentialInputTheinputcanacceptdifferentialvoltagesanywherewithinthecommonmoderangeoftheinputamplifier;orspecificallyfrom0.5Vbelowthepositivesupplyto1Vabovethenegativesupply.InthisrangethesystemhasaCMRRof86dBtypical.However,sincetheintegratoralsoswingswiththecommonmodevoltage,caremustbeexercisedtoassuretheintegratoroutputdoesnotsaturate.Aworstcaseconditionwouldbealargepositivecommon-modevoltagewithanearfullscalenegativedifferentialinputvoltage.Thenegativeinputsignaldrivestheintegratorpositivewhenmostofitsswinghasbeenusedupbythepositivecommonmodevoltage.Forthesecriticalapplicationstheintegratorswingcanbereducedtolessthantherecommended4Vfullscaleswingwithsomelossofaccuracy.Theintegratoroutputcanswingwithin0.3Vofeithersupplywithoutlossoflinearity.AnalogCOMMONAnalogCOMMONisusedastheinputlowreturnduringauto-zeroandde-integrate.IfINLOisdifferentfromanalogCOMMON,acommonmodevoltageexistsinthesystemandistakencareofbytheexcellentCMRRoftheconverter.However,inmostapplicationsINLOwillbesetatafixedknownvoltage(powersupplycommonforinstance).Inthisapplication,analogCOMMONshouldbetiedtothesamepoint,thusremovingthecommonmodevoltagefromtheconverter.ThereferencevoltageisreferencedtoanalogCOMMON.ReferenceThereferenceinputmustbegeneratedasapositivevoltagewithrespecttoCOMMON,DigitalSectionFigure5showstheDigitalSectionoftheICL7135.TheICL7135includesseveralpinswhichallowittooperateconvenientlyinmoresophisticatedsystems.Theseinclude:Run/HOLD(Pin25)Whenhigh(oropen)theA/Dwillfree-runwithequallyspacedmeasurementcyclesevery40,002clockpulses.Iftakenlow,theconverterwillcontinuethefullmeasurementcyclethatitisdoingandthenholdthisreadingaslongasR/Hisheldlow.Ashortpositivepulse(greaterthan300ns)willnowinitiateanewmeasurementcycle,beginningwithbetween1and10,001countsofautozero.Ifthepulseoccursbeforethefullmeasurementcycle(40,002counts)iscompleted,itwillnotberecognizedandtheconverterwillsimplycompletethemeasurementitisdoing.Anexternalindicationthatafullmeasurementcyclehasbeencompletedisthatthefirststrobepulse(seebelow)willoccur101countsaftertheendofthiscycle.Thus,ifRun/HOLDislowandhasbeenlowforatleast101counts,theconverterisholdingandreadytostartanewmeasurementwhenpulsedhigh.STROBE(Pin26)ThisisanegativegoingoutputpulsethataidsintransferringtheBCDdatatoexternallatches,UARTs,ormicroprocessors.Thereare5negativegoingSTROBEpulsesthatoccurinthecenterofeachofthedigitdrivepulsesandoccuronceandonlyonceforeachmeasurementcyclestarting101clockpulsesaftertheendofthefullmeasurementcycle.Digit5(MSD)goeshighattheendofthemeasurementcycleandstaysonfor201counts.Inthecenterofthisdigitpulse(toavoidraceconditionsbetweenchangingBCDanddigitdrives)thefirstSTROBEpulsegoes1negativefor1/2clockpulsewidth.Similarly,afterdigit5,digit24goeshigh(for200clockpulses)and100pulseslatertheSTROBEgoesnegativeforthesecondtime.Thiscontinuesthroughdigit1(LSD)whenthefifthandlastSTROBEpulseissent.Thedigitdrivewillcontinuetoscan(unlesstheprevioussignalwasoverrange)butnoadditionalSTROBEpulseswillbesentuntilanewmeasurementisavailable.BUSY(Pin21)BUSYgoeshighatthebeginningofsignalintegrateandstayshighuntilthefirstclockpulseafterzerocrossing(orafterendofmeasurementinthecaseofanoverrange).Theinternallatchesareenabled(i.e.,loaded)duringthefirstclockpulseafterbusyandarelatchedattheendofthisclockpulse.Thecircuitautomaticallyrevertstoauto-zerowhennotBUSY,soitmayalsobeconsidereda(Zl+AZ)signal.AverysimplemeansfortransmittingthedatadownasinglewirepairfromaremotelocationwouldbetoANDBUSYwithclockandsubtract10,001countsfromthenumberofpulsesreceived-asmentionedpreviouslythereisone“NO-count”pulseineachreferenceintegratecycle.OVERRANGE(Pin27)Thispingoespositivewhentheinputsignalexceedstherange(20,000)oftheconverter.TheoutputF/FissetattheendofBUSYandisresettozeroatthebeginningofreferenceintegrateinthenextmeasurementcycle.UNDERRANGE(Pin28)Thispingoespositivewhenthereadingis9%ofrangeorless.TheoutputF/FissetattheendofBUSY(ifthenewreadingis1800orless)andisresetatthebeginningofsignalintegrateofthenextreading.POLARlTY(Pin23)Thispinispositiveforapositiveinputsignal.Itisvalidevenforazeroreading.Inotherwords,+0000meansthesignalispositivebutlessthantheleastsignificantbit.Theconvertercanbeusedasanulldetectorbyforcingequalfrequencyof(+)and(-)readings.Thenullatthispointshouldbelessthan0.1LSB.Thisoutputbecomesvalidatthebeginningofreferenceintegrateandremainscorrectuntilitisrevalidatedforthenextmeasurement.DigitDrives(Pins12,17,18,19and20)Eachdigitdriveisapositivegoingsignalthatlastsfor200clockpulses.ThescansequenceisD5(MSD),D4,D3,D2,andD1(LSD).Allfivedigitsarescannedandthisscaniscontinuousunlessanoverrangeoccurs.ThenalldigitdrivesareblankedfromtheendofthestrobesequenceuntilthebeginningofReferenceIntegratewhenD5willstartthescanagain.Thiscangiveablinkingdisplayasavisualindicationofoverrange.BCD(Pins13,14,15and16)TheBinarycodedDecimalbitsB8,B4,B2,andB1arepositivelogicsignalsthatgoonsimultaneouslywiththedigitdriversignal.ComponentValueSelectionForoptimumperformanceoftheanalogsection,caremustbetakenintheselectionofvaluesfortheintegratorcapacitorandresistor,auto-zerocapacitor,referencevoltage,andconversionrate.Thesevaluesmustbechosentosuittheparticularapplication.IntegratingResistorTheintegratingresistorisdeterminedbythefullscaleinputvoltageandtheoutputcurrentofthebufferusedtochargetheintegratorcapacitor.BoththebufferamplifierandtheintegratorhaveaclassAoutputstagewith100Aofquiescentcurrent.Theycansupply20Aofdrivecurrentwithnegligiblenon-linearity.Valuesof5Ato40Agivegoodresults,withanominalof20A,andtheexactvalueofintegratingresistormaybechosen.IntegratingCapacitorTheproductofintegratingresistorandcapacitorshouldbeselectedtogivethemaximumvoltageswingwhichensuresthatthetolerancebuilt-upwillnotsaturatetheintegratorswing(approx.0.3Vfromeithersupply).For+5VsuppliesandanalogCOMMONtiedtosupplyground,a+3.5Vto+4Vfullscaleintegratorswingisfine,and0.47Fisnominal.Ingeneral,thevalueofCINTisgiven.Averyimportantcharacteristicoftheintegratingcapacitoristhatithaslowdielectricabsorptiontopreventroll-overorratiometricerrors.Agoodtestfordielectricabsorptionistousethecapacitorwiththeinputtiedtothereference.Thisratiometricconditionshouldreadhalfscale0.9999,andanydeviationisprobablyduetodielectricabsorption.Polypropylenecapacitorsgiveundetectableerrorsatreasonablecost.Polystyreneandpolycarbonatecapacitorsmayalsobeusedinlesscriticalapplications.Auto-ZeroandReferenceCapacitorThephysicalsizeoftheauto-zerocapacitorhasaninfluenceonthenoiseofthesystem.Alargercapacitorvaluereducessystemnoise.Alargerphysicalsizeincreasessystemnoise.Thereferencecapacitorshouldbelargeenoughsuchthatstraycapacitancetogroundfromitsnodesisnegligible.Thedielectricabsorptionofthereferencecapandauto-zerocapareonlyimportantatpower-onorwhenthecircuitisrecoveringfromanoverload.Thus,smallerorcheapercapscanbeusedhereifaccuratereadingsarenotrequiredforthefirstfewsecondsofrecovery.ReferenceVoltageTheanaloginputrequiredtogenerateafullscaleoutputisREFINV2Thestabilityofthereferencevoltageisamajorfactorintheoverallabsoluteaccuracyoftheconverter.Forthisreason,itisrecommendedthatahighqualityreferencebeusedwherehigh-accuracyabsolutemeasurementsarebeingmade.RolloverResistorandDiodeAsmallrollovererroroccursintheICL7135,butthiscanbeeasilycorrectedbyaddingadiodeandresistorinseriesbetweentheINTegratorOUTputandanalogCOMMONorground.Thevalueshownintheschematicsisoptimumfortherecommendedconditions,butifintegratorswingorclockfrequencyismodified,adjustmentmaybeneeded.Thediodecanbeanysilicondiodesuchas1N914.Thesecomponentscanbeeliminatedifrollovererrorisnotimportantandmaybealteredinvaluetocorrectother(small)sourcesofrolloverasneeded.MaxClockFrequencyThemaximumconversionrateofmostdual-slopeA/Dconvertersislimitedbythefrequencyresponseofthecomparator.Thecomparatorinthiscircuitfollowstheintegratorrampwitha3sdelay,andataclockfrequencyof160kHz(6speriod)halfofthefirstreferenceintegrateclockperiodislostindelay.Thismeansthatthemeterreadingwillchangefrom0to1witha50Vinput,1to2witha150Vinput,2to3witha250Vinput,etc.Thistransitionatmid-pointisconsidereddesirablebymostusers;however,iftheclockfrequencyisincreasedappreciablyabove160kHz,theinstrumentwillflash“1”onnoisepeaksevenwhentheinputisshorted.Formanydedicatedapplicationswheretheinputsignalisalwaysofonepolarity,thedelayofthecomparatorneednotbealimitation.Sincethenon-linearityandnoisedonotincreasesubstantiallywithfrequency,clockratesofupto1MHzmaybeused.Forafixedclockfrequency,theextracountorcountscausedbycomparatordelaywillbeconstantandcanbesubtractedoutdigitally.Theclockfrequencymaybeextendedabove160kHzwithoutthiserror,however,byusingalowvalueresistorinserieswiththeintegratingcapacitor.Theeffectoftheresistoristointroduceasmallpedestalvoltageontotheintegratoroutputatthebeginningofthereferenceintegratephase.Bycarefulselectionoftheratiobetweenthisresistorandtheintegratingresistor(afewtensofohmsintherecommendedcircuit),thecomparatordelaycanbecompensatedandthemaximumclockfrequencyextendedbyapproximatelyafactorof3.Athigherfrequencies,ringingandsecondorderbreakswillcausesignificantnon-linearitiesinthefirstfewcountsoftheinstrument.SeeApplicationNoteAN017.Theminimumclockfrequencyisestablishedbyleakageontheauto-zeroandreferencecaps.Withmostdevices,measurementcyclesaslongas10sgivenomeasurableleakageerror.Toachievemaximumrejectionof60Hzpickup,thesignalintegratecycleshouldbeamultipleof60Hz.Oscillatorfrequenciesof300kHz,200kHz,150kHz,120kHz,100kHz,40kHz,33kHz,etc.shouldbeselected.For50Hzrejection,oscillator31frequenciesof250kHz,166kHz,125kHz,100kHz,etc.wouldbesuitable.Notethat2100kHz(2.5readings/sec)willrejectboth50Hzand60Hz.Theclockusedshouldbefreefromsignificantphaseorfrequencyjitter.Severalsuitablelow-costoscillatorsareshownintheTypicalApplicationssection.Themultiplexedoutputmeansthatifthedisplaytakessignificantcurrentfromhelogicsupply,theclockshouldhavegoodPSRR.Zero-CrossingFlip-FlopTheflip-flopinterrogatesthedataonceeveryclockpulseafterthetransientsofthepreviousclockpulseandhalf-clockpulsehavedieddown.Falsezero-crossingscausedbyclockpulsesarenotrecognized.Ofcourse,theflip-flopdelaysthetruezero-crossingbyuptoonecountineveryinstance,andifacorrectionwerenotmade,thedisplaywouldalwaysbeonecounttoohigh.Therefore,thecounterisdisabledforoneclockpulseatthebeginningofphase3.Thisone-countdelaycompensatesforthedelayofthezero-crossingflip-flop,andallowsthecorrectnumbertobelatchedintothedisplay.Similarly,aone-countdelayatthebeginningofphase1givesanoverloaddisplayof0000insteadof0001.Nodelayoccursduringphase2,sothattrueratiometricreadingsresult.EvaluatingTheErrorSourcesErrorsfromthe”ideal”cyclearecausedby:1.Capacitordroopduetoleakage.2.Capacitorvoltagechangeduetocharge“suck-out”(thereverseofchargeinjection)whentheswitchesturnoff.3.Non-linearityofbufferandintegrator.4.High-frequencylimitationsofbuffer,integrator,andcomparator.5.Integratingcapacitornon-linearity(dielectricabsorption).6.ChargelostbyinchargingRFCSTRAYC7.ChargelostbyandtochargeAZINEacherrorisanalyzedforitserrorcontributiontotheconverterinapplicationnoteslistedonthebackpage,specificallyApplicationNoteAN017andApplicationNoteAN032.NoiseThepeak-to-peaknoisearoundzeroisapproximately15V(peak-to-peakvaluenotexceeded95%ofthetime).Nearfullscale,thisvalueincreasestoapproximately30V.Muchofthenoiseoriginatesintheauto-zeroloop,andisproportionaltotheratiooftheinputsignaltothereference.AnalogAndDigitalGroundsExtremecaremustbetakentoavoidgroundloopsinthelayoutofICL7135circuits,especiallyinhigh-sensitivitycircuits.Itismostimportantthatreturncurrentsfromdigitalloadsarenotfedintotheanaloggroundline.PowerSuppliesTheICL7135isdesignedtoworkfrom+5Vsupplies.However,inselectedapplicationsnonegativesupplyisrequired.Theconditionstouseasingle+5Vsupplyare:1.Theinputsignalcanbereferencedtothecenterofthecommonmoderangeoftheconverter.2.Thesignalislessthan+1.5V.外文资料译文ICL713541/2Digit,BCDOutput,A/DConverterICL7135是由INTERSIL公司生产的高精度A/D转换器，它的双斜率积分转换可靠性可达到在20,000计数中有+1的误差，另外加上它的数字躯动输出端以及多路复用的二一十进制码(BCD)输出端，就可以应用于数字电压表，数字电流表的显示。它的大部分电路都集中在CMOS工艺的集成芯片中，只要附加译码器，数码显示器，驱动器及参考电压和时钟，就可组成一个满量程为2V的数字电压表，它具有自动进行调零操作，自动极性转换等功能。ICL7135具有高精确度，通用性和经济等优点。零点误差小于10v.零点漂移小于1V/.低输入电流(小于10PA)使源阻抗误差为最小。翻转误差限制在士1计数值.BUSY,STROBE,RUN/BOLD,OVERRANGE以及UNDERRANGE控制信号支持基于微处理器的测量系统。控制信号也能支持通过通用异步接收器发送器(UART)进行数据传送的远程数据采集系统。特点：*在20,000计数中有+1的误差（2V满量程）*0v输入零读数*IPA典型输入电流*真正差分输入*需要的唯一参考电压*Overrange和Underrange信号的自动范围能力*TTL兼容性*控制信号允许与UARTS或微处理器接口*多路复用二十进制代码(BCD)输出*无铅工艺详细描写模拟部分每个测量周期被划分成四个阶段。他们是(1)自动调零(AZ)，(2)信号积分(INT)，(3)去积分(DE)和(4)积分器返回零(Zl)。自动调零在自动调零阶段，处理3件事。第一，自动调零相.内部IN+和IN-输入与引脚断开且在内部连接至模拟地。第二，基准电容被充电至基准电压。第三，系统接成闭环。自动调零电容被充电以补偿缓冲放大器。积分器和比较器的失调电压。自动调零精度仅受系统噪声的限制。以输入为基准的总失调小于10V。信号积分在信号积分阶段，自动调零环路被打开，内部短路被移除。内部的IN+和IN-输入被连接至外部引脚。在固定的时间周期内这些输入端之间的差分电压被积分。这些差分电压可以工作在一个广泛的共模范围内。如果，在另一方面，当输入信号相对于转换器电源不反相时。IN-连接至模拟地以建立正确的共模电压。在这一相完成的基础上。输入信号的极性被记录。去积分第三阶段为去积分或参考积分阶段，基准用于完成去积分任务，内部IN-在内部连接至模拟地,IN+跨接至先前已充电的基准电容。所记录的输入信号的极性确保以正确的极性连接电容以便积分器输出极性回到零，输出返回至零所需的时间正比于输入信号的幅度，返回时间显示为数宇读数并由等式10000（VIN/VREF）确定。满度或最大转换值发生在VID等于两倍VREF时。积分器返回零.最后一个阶段为积分返回零阶段，第一，内部的IN-连接到模拟地。第二，系统接成闭环以便使积分器输出返回到零。通常这一相需要100至200个时钟脉冲。但是在超范围转换后，需要6200个脉冲。输入信号范围输入信号可以接受任何的差分信号，只要输入放大器的共模范围从负电源电压加1V延展到正电源电压减0.5V。在此范围内.共模抑制比（CMRR）的典型值为86dB。差分和共模电压二者均使积分器的输出摆动。因此.必须小心确保积分器的输出不变成饱和。最坏的情况是出现大量正的共模电压与附近的负的差分输入电压。负的输入信号积分到达正时，其大部分的摆动已消耗掉共模电压。为这些重要应用与一些精确损失，建议使用的4V全方位摆动可以减少积分器摆动。积分器输出可能在任一输入之内达到0.3V摆动，不会产生线性损失。模拟公共端在自动调零.去积分以及积分器返零相期间内，模拟公共端连接到内部IN-。在信号积分相期间内，IN-连接到与模拟公共端不同的电压.此时所产生的共模电压被放大器抑制，但是.在大多数应用中.IN-被置于已知的固定电压(即，例如电源的公共端).在这种应用中.模拟公共端应当连接到同样的点.于是从转换器除去模电压。用这种方式消除共模电压可稍微提高转换精度。基准基准电压相对于模拟公共端为正。转换结果的精度取决于基准的质量。因此.为了得到高精度的转换，应当使用高质量的基准数字部分所显示为icl7135的数字部分。icl7135的引脚允许其方便地应用在更复杂的系统。这些包括：RUN/HOLD输入（25脚）当RUN/HOLD端为高电平或开路时。器件连续地每40002个时钟脉冲完成测量周期。当此输入拉至低电平时，积分电路继续完成正在进行的测量周期。然后。只要引脚保持低电平，它便保持转换的读数。当测量周期完成之后引脚保持低电平时。短的正脉冲(大于300ns)将启动新的测量周期，它的开始以1和10001个计数脉冲的自动归零阶段为准。当此正脉冲发生于测量周期（40002个脉冲）完成之前时.它将不被识别。第一个STROBE脉冲发生于测量周期结束之后101计数处。它是测量周期完成的指示。因此。如果RUN/HOLD为低电平，且在积分完成后第101个计数以后，即在第一个STROBE脉冲之后。正脉冲可用于触发新的测量的开始。STROBE（26脚）来自此输入端的负向脉冲把BCD转换数据传送到外部锁存器、UART或微处理器在测量周朝结束时。STROBE变为高电平并保持高电平达加201个计数值的时间，最高有效数字(MSD)BCD位放置在BCD端。在开始101个计数之后。在输出D1-5变为高电平期间内的中途。STROBE变为低电平达1/2时钟脉冲宽度。在D5高电平脉冲的中间点放置STROBE脉冲允许用低电平或边沿把信息锁存入外部器件。这种STROBE脉冲的放置还确保第二个MSD的BCD位也不竞争BCD线并且确保正确位的锁存。对于第二个MSD和以D4输出将重复以上过程。类似地。直至最低有效数字(LSD)将重复此过程。因此。输入D5至D1和BCD线继续扫描而不包括STROBE脉冲。这种后续的连续扫描使转换结果连续被显示。当超范围(over-range)条件发生时，这种后续扫描将不发生。BUSY(21脚)在信号积分相开始时BUSY(忙)输出变为高电平。BUSY将保持高电平直到零穿越(Zerocrossing)之后的第一个时钟脉冲或超范围条件发生时的测量周朝结束时，利用BUSY端串行发送转换结果是可能的，通过把BUSY和CLOCK信号相“与”(AND)并发送“与”的结果使可完成串行发送。所发送的输出包括发生在信号积分相内10,001个时钟脉冲以及发生在去积分(deintegrate)相期间内的时钟脉冲数。从总的时钟脉冲数减去10001可以得到转换结果。OVERRANGE(27脚)当输入信号大于2V满量程时，该管脚信号变为高电平。也就是说，当超范围(overrange)条件发生时，在测量周朝结束时BUSY(忙)信号变