FPGA实验计数器设计实验.doc

哈尔滨理工大学软件学院实验报告课 程 FPGA题 目 实验二 计数器设计实验班 级 集成12-2班专 业 集成电路设计与集成系统 学 生 学 号 1214020227 2014年 10 月15日实验二 计数器设计实验实验目的： 学习计数器的设计、仿真和硬件测试方法。实验内容及步骤： 1.使用Verilog HDL设计2位 16进制计数器,由DE2的KEY0输入计数值，在HEX1，HEX0上显示计数值。 2.使用嵌入式逻辑分析仪进行仿真； 3.将实验程序下载到DE2运行。实验注意事项：去抖动DE2按键电路图实验程序：module counting(clk,reset,k,h1,h2);input k,reset,clk;output 6:0h1,h2;reg 7:0count;reg key;reg 6:0h1,h2;reg 10:0clock=11b0; always(posedge clk)begin if(k) / k is the input Key0 begin key=1; clock=0; endelse begin clock=clock+1; / if clock still isnt 2000 ,then the next all don,t excutive if(clock=1000) / so continue came back until up to 2000 begin clock=11b0; key=0; / to produce a negadge as a senstive pinend endendalways(negedge key or negedge reset) begin if(reset=0) count=0; else count=count+1b1;endalways(count)begin case(count3:0) 4b0000:h1=7b1000000;4b0001:h1=7b1111001;4b0010:h1=7b0100100;4b0011:h1=7b0110000;4b0100:h1=7b0011001;4b0101:h1=7b0010010;4b0110:h1=7b0000010;4b0111:h1=7b1111000;4b1000:h1=7b0000000;4b1001:h1=7b0010000;4b1010:h1=7b0001000;4b1011:h1=7b0000011;4b1100:h1=7b1000110;4b1101:h1=7b0100001;4b1110:h1=7b0000110;4b1111:h1=7b0001110;default : h1=7b1000000;endcasecase(count7:4) 4b0000:h2=7b1000000;4b0001:h2=7b1111001;4b0010:h2=7b0100100;4b0011:h2=7b0110000;4b0100:h2=7b0011001;4b0101:h2=7b0010010;4b0110:h2=7b0000010;4b0111:h2=7b1111000;4b1000:h2=7b0000000;4b1001:h2=7b0010000;4b1010:h2=7b0001000;4b1011:h2=7b0000011;4b1100:h2=7b1000110;4b1101:h2=7b0100001;4b1110:h2=7b00001