3杏林毕业设计(论文)附件.doc

南通大学杏林学院 本科毕业设计（论文）附 件题目V2O5纳米结构气相制备及其Li电池性能研究 学生姓名： 陈益栋 专 业： 电子信息工程（电子科学与技术）指导教师： 尹海宏 讲师 南通大学杏林学院毕业设计（论文）立题卡课题名称V2O5纳米结构气相制备及其Li电池性能研究出题人尹海宏课题表述（简述课题的背景、目的、意义、主要内容、完成课题的条件、成果形式等）随着科技的发展，纳米材料因其特有的性质被使用在各个领域，锂电池也开始从纳米材料着手制作正负极。 此次我们是利用气相制备V2O5纳米结构，了解其结构和表征。再使用此材料制作出锂电池，研究锂电池的性能。课题来源科研课题类别毕业设计该课题对学生的要求1. 掌握纳米材料和锂电池等方面的相关知识2. 具备一定的外文文献阅读能力3. 能够了解气相制备原理和锂电池各方面性能，完成毕业设计论文。学系意见 同意立题（）不同意立题（） 学系主任签名：_ 2012 年1 月 12 日注：1、此表一式三份，学系、教务处、学生档案各一份。 2、课题来源是指：1.科研，2.社会生产实际，3. 其他。3、课题类别是指：1.毕业论文，2.毕业设计。4、学系意见：在组织专业指导委员会审核后，就该课题的工作量大小，难易程度及是否符合专业培养目标和要求等内容提出具体的意见和建议。南通大学杏林学院毕业设计（论文）任务书题目： V2O5纳米结构气相制备及其Li电池性能研究姓 名 陈益栋 专 业 电子信息工程（电子科学与技术）班 级 电子081 指导教师 尹海宏 讲师 发任务书日期 2012 年 1 月 12 日课题的内容和要求（研究内容、研究目标和解决的关键问题）研究内容：本课题是研究五氧化二钒纳米材料的气相制备，并且利用这种材料制备出锂离电池，同时对其性能进行检测。研究目标：研究在不同衬底温度下，五氧化二钒纳米结构的表征，解决多次充放电后，锂电池的性能。解决的关键问题：锂离电池的制备，五氧化二钒的气相制备课题的研究方法和技术路线研究方法：改变衬底温度，多次充放电实验技术路线：通过气相制备出纳米结构的五氧化二钒，然后制备出锂离电池。再通过多次充放电实验得出结论。基础条件 已学习和掌握气相制备，锂电池各方面性能等方面的相关知识，具有动手制备能力，并有相关的文献资料，具备完成该课题的基本条件。参考文献1詹晖,周运鸿, 电源技术M,1999,23(3),S103-S105.2樊恺郁 新能源汽车行业,审视全球锂电发展格局及趋势R ,2005,5-10.3高阳,谢晓华,解晶莹等. 锂离子蓄电池电解液研究进展J.电源技术,2003,27(5): 479483.4申泮文,车云霞,裕基等, 无机化学丛书第八卷,钛分族,钒分族M.北京:科学出版社,1998, 173-281.5 Whittingham M.S.The role of ternary phases in cathode reactionsJ.J Electrochem Soc, 1976,123: 315320.6刘景,温兆银,吴梅梅, 无机化学报J 纳米无机材料,2002 ,17(1):1-9.7 Lijm, Rui A. S, Optical and structural properties of vanadium pentoxide films prepared by d.c. reactive magnetron sputtering J. ThinSolid Films, 2006, 515: 195200.8 Nicolap M.W, Klau S .W, et al. Local structure of nanoscopic materials: V2O5 nanorodsand nanowires J. Nano Lett, 2003, 3(8):11311134.9Dmitry A. S, Tatiana L .K, Alexander M .S, et al. Impedan cespectroscopy study of lithium ion diffusion in a new cathode materialbased on vanadium pentoxide J. Mendeleev Commun, 2010, 20:910.10 Feng C.Q, Wang S .Y, Zeng R, et al. Synthesis of spherical porous vanadium pentoxide and its electrochemical properties J. PowerSources, 2008, 184: 485488.11 Mohan V.M,Hub. Synthesis, structural, and electrochemical performance of V2O5 nanotubes as cathode material for lithium batteryJ.J Appl Electrochem,2009,39: 20012006本课题必须完成的任务（1）写开题报告；（2）完成与课题相关的英文翻译；（3）完成与课题相关的研究和材料表征；（4）撰写毕业论文。成果形式（1）英文翻译；（2）开题报告；（3）毕业论文。进度计划起讫日期工作内容备 注3.53.20查阅资料、英文翻译3.214.19通过气相法制备五氧化二钒纳米材料4.205.10材料的XRD以及SEM表征5.116.7修改完善毕业论文，准备毕业答辩学 系 审 核 意 见该课题符合电子科学与技术专业培养目标和要求，能结合实际进行研究，工作量适中，难易程度适中，满足本科毕业设计要求。 系主任签名： 2012 年 1 月 9日南通大学杏林学院本科生毕业设计（论文）开题报告学生姓名陈益栋学 号0811063023专业电子信息工程（电子科学与技术）课题名称V2O5纳米结构气相制备及其Li电池性能研究阅读文献情 况国内文献5 篇开题日期2012年 03月18日阅读文献国外文献6篇开题地点12#615一 文献综述与调研报告：（阐述课题研究的现状及发展趋势，本课题研究的意义和价值、参考文献）本课题研究的现状及发展趋势：随着科技的发展，锂离电池的优越性也显现出来，锂离子电池具有较高的电压、比能量和无记忆效应等特点。与铅蓄电池相比，其循环寿命长、安全性能好。在过去，LiCoO2、LiNiO2 等作为锂离电池的正极材料被广泛使用。但是这些材料都存在着存在价格贵、资源有限、结构不稳定、合成过程困难等缺点。而钒是一种成本较为低廉的富产元素，近年来五氧化二钒(V2O5)作为一种锂离子电池的正极材料已经引起人们极大的关注。目前我们研究的课题即如何使用V2O5纳米材料制备出锂离电池，本研究采用极其简单的气相制备合成了具有微纳尺寸的V2O5纳米棒正极材料。将其组装成扣式电池，采用恒电流充放电等技术研究了材料的电化学性能。在未来，越来越多的V2O5纳米材料制备出的锂离电池将会取代现有的锂离电池，成为主流产品。本课题研究的意义和价值：由于锂电池都具有额定电压，使用寿命和充放电次数限制。我们通过数百到上千次的由充满电到放空电来检测出自己所制备的锂离电池与标准是否相差无几。参考文献：1詹晖,周运鸿, 电源技术M,1999,23(3):S103-S105.2樊恺郁 新能源汽车行业,审视全球锂电发展格局及趋势R ,2005,5-10.3高阳,谢晓华,解晶莹等. 锂离子蓄电池电解液研究进展J.电源技术,2003,27(5): 479483.4申泮文,车云霞,裕基等, 无机化学丛书第八卷,钛分族,钒分族M.北京:科学出版社,1998, 173-281.5 Whittingham M. S. The role of ternary phases in cathode reactionsJ. J Electrochem Soc, 1976, 123: 315320.6刘景,温兆银,吴梅梅, 无机化学报J纳米无机材料,2002 ,17(1):1-9.7 Lijm, Rui A. S, Optical and structural properties of vanadium pentoxide films prepared by d.c. reactive magnetron sputtering J. ThinSolid Films, 2006, 515: 195200.8 Nicolap M.W, Klau S .W, et al. Local structure of nanoscopic materials: V2O5 nanorodsand nanowires J. Nano Lett, 2003, 3(8):11311134.9Dmitry A. S, Tatiana L .K, Alexander M .S, et al. Impedan cespectroscopy study of lithium ion diffusion in a new cathode materialbased on vanadium pentoxide J. Mendeleev Commun, 2010, 20:910.10 Feng C.Q, Wang S .Y, Zeng R, et al. Synthesis of spherical porous vanadium pentoxide and its electrochemical properties J. PowerSources, 2008, 184: 485488.11 Mohan V .M，Hub. Synthesis, structural, and electrochemical performance of V2O5 nanotubes as cathode material for lithium batteryJ. J Appl Electrochem, 2009, 39: 20012006二 本课题的基本内容，预计解决的难题基本内容：本课题是研究五氧化二钒纳米材料的气相制备，并且利用这种材料制备出锂离电池，同时对其性能进行检测。预计解决的难题：锂离电池的制备，五氧化二钒的气相制备三 课题的研究方法、技术路线研究方法：不同衬底温度制备五氧化二钒，多次充放电测试。技术路线：通过气相制备出纳米结构的五氧化二钒，然后制备出锂离电池。再通过多次充放电实验得出结论。四 研究工作条件和基础1、已学习和掌握纳米材料和锂电池各方面性能的相关知识；2、有相关的文献资料；3、具备有相应的动手操作能力。五、进度计划起讫日期工作内容3.53.20查阅资料、英文翻译。3.214.19通过气相法制备五氧化二钒纳米材料 4.205.10材料的XRD以及SEM表征5.116.7修改完善毕业论文，准备毕业答辩。论文阶段完成日期文献调研完成日期3.20论文实验完成日期5.23撰写论文完成日期5.31评议答辩完成日期6.13指导教师评语该同学对材料制备和表征以及材料性能有大致了解，文献查阅较多，整体思路明确，方法可行，同意开题。 导师签名： 2012年 3 月 18 日学系意见通过开题（）开题不通过（） 学系主任签名： 2012年 3 月 18 日南通大学杏林学院毕业设计（论文）中期检查表学系：电子信息 专业：电子信息工程（电子科学与技术） 填表日期：2012年4月20日毕业设计（论文）题目：V2O5纳米结构气相制备及其Li电池性能研究学生姓名： 陈益栋学号：0811063023文献、资料检索阅读：中文5篇，外文6篇；是否具备独立查阅文献资料的能力是。开题完成情况：好（）较好（）一般（ ） 差（）未完成（）外文资料翻译情况：好（）较好（）一般（ ）差（）未完成（）学习态度: 好（）较好（）一般（）差（）出勤情况：出勤记载是否详实是；请假次数：0，缺席次数：0。毕业设计（论文）的进度（与任务书进度相对照）：正常（）过快（）偏慢（）中期检查综合评价：该同学开题报告以及翻译均合格。气相制备出的五氧化二钒纳米结构材料有缺陷。整体表现良好。存在问题和改进措施：存在问题：气相制备五氧化二钒纳米结构步骤上有问题。改进措施：改变炉管中心温度中期检查结论：好（）较好（）一般（）差（）注：1本表由检查教师填写，交系保存备查，最终归入学生毕业设计（论文）档案；2本表仅供参考，各系根据检查需要，可对检查内容进行必要的调整。检查教师： 学系主任： 南通大学杏林学院毕业设计（论文）成果验收表学系：电子信息 专业：电子信息工程（电子科学与技术） 填表日期：2012年5月31日毕业设计（论文）题目：V2O5纳米结构气相制备及其Li电池性能研究学生姓名： 陈益栋学号：0811063023提交验收的毕业设计（论文）成果：1.一篇英文翻译。2一种五氧化二钒纳米结构制备方法及其Li+电池的性能研究。3毕业设计论文。毕业设计（论文）成果特色和创新点：用气相法成功制备出了五氧化二钒纳米结构并进行了表征，同时对锂电池的性能进行了检测。验收小组意见：经验收小组现场对论文，材料表征结果进行了验收，该生已经基本完成课题研究任务，同意其参加毕业论文答辩。验收小组组长（签章）_ 2012 年 5 月 31 日注：1本表验收小组意见一栏由验收小组组长填写，其余内容由学生申报填写。2本表最终归入学生毕业设计（论文）档案。南通大学杏林学院 本科毕业设计（论文）英文原文及译文学生姓名： 陈益栋 专 业：电子信息工程（电子科学与技术）指导教师： 尹海宏 完成日期： 2012.4.31 Programmable Logic Controllers (PLCs)1 。About Programmable Logic Controllers (PLCs)PLCs (programmable logic controllers) are the control hubs for a wide variety of automated systems and processes. They contain multiple inputs and outputs that use transistors and other circuitry to simulate switches and relays to control equipment. They are programmable via software interfaced via standard computer interfaces and proprietary languages and network options.Programmable logic controllers I/O channel specifications include total number of points, number of inputs and outputs, ability to expand, and maximum number of channels. Number of points is the sum of the inputs and the outputs. PLCs may be specified by any possible combination of these values. Expandable units may be stacked or linked together to increase total control capacity. Maximum number of channels refers to the maximum total number of input and output channels in an expanded system. PLC system specifications to consider include scan time, number of instructions, data memory, and program memory. Scan time is the time required by the PLC to check the states of its inputs and outputs. Instructions are standard operations (such as math functions) available to PLC software. Data memory is the capacity for data storage. Program memory is the capacity for control software. Available inputs for programmable logic controllers include DC, AC, analog, thermocouple, RTD, frequency or pulse, transistor, and interrupt inputs. Outputs for PLCs include DC, AC, relay, analog, frequency or pulse, transistor, and triac. Programming options for PLCs include front panel, hand held, and computer. Programmable logic controllers use a variety of software programming languages for control. These include IEC 61131-3, sequential function chart (SFC), function block diagram (FBD), ladder diagram (LD), structured text (ST), instruction list (IL), relay ladder logic (RLL), flow chart, C, and Basic. The IEC 61131-3 programming environment provides support for five languages specified by the global standard: Sequential Function Chart, Function Block Diagram, Ladder Diagram, Structured Text, and Instruction List. This allows for multi-vendor compatibility and multi-language programming. SFC is a graphical language that provides coordination of program sequences, supporting alternative sequence selections and parallel sequences. FBD uses a broad function library to build complex procedures in a graphical format. Standard math and logic functions may be coordinated with customizable communication and interface functions. LD is a graphic language for discrete control and interlocking logic. It is completely compatible with FBD for discrete function control. ST is a text language used for complex mathematical procedures and calculations less well suited to graphical languages. IL is a low-level language similar to assembly code. It is used in relatively simple logic instructions. Relay Ladder Logic (RLL), or ladder diagrams, is the primary programming language for programmable logic controllers (PLCs). Ladder logic programming is a graphical representation of the program designed to look like relay logic. Flow Chart is a graphical language that describes sequential operations in a controller sequence or application. It is used to build modular, reusable function libraries. C is a high level programming language suited to handle the most complex computation, sequential, and data logging tasks. It is typically developed and debugged on a PC. BASIC is a high level language used to handle mathematical, sequential, data capturing and interface functions. Programmable logic controllers can also be specified with a number of computer interface options, network specifications and features. PLC power options, mounting options and environmental operating conditions are all also important to consider.2 。INTRODUCTIONFor simple programming the relay model of the PLC is sufficient. As more complex functions are used the more complex VonNeuman model of the PLC must be used. A VonNeuman computer processes one instruction at a time. Most computers operate this way, although they appear to be doing many things at once. Consider the computer components shown in Figure 1.Figure 1 1 Simplified Personal Computer ArchitectureInput is obtained from the keyboard and mouse, output is sent to the screen, and the disk and memory are used for both input and output for storage. (Note: the directions of these arrows are very important to engineers, always pay attention to indicate where information is flowing.) This figure can be redrawn as in Figure 2 to clarify the role of inputs and outputs.Figure 2 An Input-Output Oriented ArchitectureIn this figure the data enters the left side through the inputs. (Note: most engineering diagrams have inputs on the left and outputs on the right.) It travels through buffering circuits before it enters the CPU. The CPU outputs data through other circuits. Memory and disks are used for storage of data that is not destined for output. If we look at a personal computer as a controller, it is controlling the user by outputting stimuli on the screen, and inputting responses from the mouse and the keyboard.A PLC is also a computer controlling a process. When fully integrated into an application the analogies become;inputs - the keyboard is analogous to a proximity switchinput -circuits - the serial input chip is like a 24Vdc input cardcomputer - the 686 CPU is like a PLC CPU unitoutput - circuits - a graphics card is like a triac output cardoutputs - a monitor is like a lightstorage - memory in PLCs is similar to memories in personal computersIt is also possible to implement a PLC using a normal Personal Computer, although this is not advisable. In the case of a PLC the inputs and outputs are designed to be more reliable and rugged for harsh production environments.3 。 OPERATION SEQUENCEAll PLCs have four basic stages of operations that are repeated many times per second. Initially when turned on the first time it will check its own hardware and software for faults. If there are no problems it will copy all the input and copy their values into memory, this is called the input scan. Using only the memory copy of the inputs the ladder logic program will be solved once, this is called the logic scan. While solving the ladder logic the output values are only changed in temporary memory. When the ladder scan is done the outputs will be updated using the temporary values in memory, this is called the output scan. The PLC now restarts the process by starting a self check for faults. This process typically repeats 10 to 100 times per second as is shown in Figure 3.Figure 3 PLC Scan CycleSELF TEST - Checks to see if all cards error free, reset watch-dog timer, etc. (A watchdog timer will cause an error, and shut down the PLC if not reset within a short period of time - this would indicate that the ladder logic is not being scanned normally).INPUT SCAN - Reads input values from the chips in the input cards, and copies their values to memory. This makes the PLC operation faster, and avoids cases where an input changes from the start to the end of the program (e.g., an emergency stop). There are special PLC functions that read the inputs directly, and avoid the input tables.LOGIC SOLVE/SCAN - Based on the input table in memory, the program is executed 1 step at a time, and outputs are updated. This is the focus of the later sections.OUTPUT SCAN - The output table is copied from memory to the outputchips.Thesechipsthen drive the output devices.The input and output scans often confuse the beginner, but they are important. The input scan takes a snapshot of the inputs, and solves the logic. This prevents potential problems that might occur if an input that is used in multiple places in the ladder logic program changed while half way through a ladder scan. Thus changing the behaviors of half of the ladder logic program. This problem could have severe effects on complex programs that are developed later in the book. One side effect of the input scan is that if a change in input is too short in duration, it might fall between input scans and be missed.When the PLC is initially turned on the normal outputs will be turned off. This does not affect the values of the inputs.3 。1 The Input and Output ScansWhen the inputs to the PLC are scanned the physical input values are copied into memory. When the outputs to a PLC are scanned they are copied from memory to the physical outputs. When the ladder logic is scanned it uses the values in memory, not the actual input or output values. The primary reason for doing this is so that if a program uses an input value in multiple places, a change in the input value will not invalidate the logic. Also, if output bits were changed as each bit was changed, instead of all at once at the end of the scan the PLC would operate much slower.3 。2 The Logic ScanLadder logic programs are modelled after relay logic. In relay logic each element in the ladder will switch as quickly as possible. But in a program elements can only be examines one at a time in a fixed sequence. Consider the ladder logic in Figure 4, the ladder logic will be interpreted left-to-right, top-to-bottom. In the figure the ladder logic scan begins at the top rung. At the end of the rung it interprets the top output first, then the output branched below it. On the second rung it solves branches, before moving along the ladder logic rung.Figure 4 Ladder Logic Execution SequenceThe logic scan sequence become important when solving ladder logic programs which use outputs as inputs. It also becomes important when considering output usage. Consider Figure 5, the first line of ladder logic will examine input A and set output X to have the same value. The second line will examine input B and set the output X to have the opposite value. So the value of X was only equal to A until the second line of ladder logic was scanned. Recall that during the logic scan the outputs are only changed in memory, the actual outputs are only updated when the ladder logic scan is complete. Therefore the output scan would update the real outputs based upon the second line of ladder logic, and the first line of ladder logic would be ineffective.Figure 5 A Duplicated Output Error4 。 PLC STATUSThe lack of keyboard, and other input-output devices is very noticeable on a PLC. On the front of the PLC there are normally limited status lights. Common lights indicate;power on - this will be on whenever the PLC has powerprogram running - this will often indicate if a program is running, or if no program is runningfault - this will indicate when the PLC has experienced a major hardware or software problemThese lights are normally used for debugging. Limited buttons will also be provided for PLC hardware. The most common will be a run/program switch that will be switched to program when