verilog编写的延时函数

Verilog 编写的延时函数 用 quartus 编译通过 并且用 modelsim 进行了后仿真 老师让编写一个程序实现开关的延时控制 具体要求是开关量变高电平后延时 500ms 输出波形 PWM1 变为高 在延时 500msPWM2 输出波形变为高 在延时 500msPWM3 输出变为高电平 当开关量变为低电平时 一次延时 500ms PWM3 PWM2 PWM1 一次变为高电平 源程序如下 module testosc osc in osc out clk in clk out input signal PWM1 PWM2 PWM3 sta rt signal buffer input osc in clk in input signal output PWM1 PWM2 PWM3 start output osc out clk out output signal buffer reg PWM1 PWM2 PWM3 osc out clk out start out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 out17 out18 out19 out20 out21 out22 out23 out24 out25 out26 out27 out28 out29 out 30 out31 out32 reg 10 0 count reg signal buffer initial begin PWM1 1 b0 PWM2 1 b0 PWM3 1 b0 start 1 b0 count 11 d0 signal buffer 1 b0 end always osc in begin if osc in 1 begin osc out 0 clk out 0 end else begin osc out 1 clk out 1 end end always posedge clk in begin if input signal 1 b0 begin case count 11 d0 if signal buffer 1 b1 distinguish the trigger signals start 1 b1 else start 1 b0 11 d2 PWM3 1 b0 11 d4 PWM2 1 b0 11 d6 begin PWM1 1 b0 start 1 b0 signal buffer 1 b0 remember the input signal end default begin PWM1 PWM1 PWM2 PWM2 PWM3 PWM3 end endcase end else begin case count 11 d0 if signal buffer 1 b0 start 1 b1 else start 1 b0 11 d2 PWM1 1 b1 11 d4 PWM2 1 b1 11 d6 begin PWM3 1 b1 start 1 b0 signal buffer 1 b1 end default begin PWM1 PWM1 PWM2 PWM2 PWM3 PWM3 end endcase end end always posedge clk in or negedge start if start 1 b0 count11 d1500 count 11 d0 else count count 11 d1 endmodule quartus 仿真波形 Mo