EDA课程设计 交通灯控制器.docx

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity EDA1 is port(clk,en: in std_logic; lampa,lampb: out std_logic_vector(3 downto 0); acount,bcount: out std_logic_vector(7 downto 0);end EDA1;architecture a of EDA1 is signal numa,numb: std_logic_vector(7 downto 0); signal tempa,tempb: std_logic; signal statea,stateb: std_logic_vector(2 downto 0); signal ared,bred,agreen,bgreen,ayellow,byellow,aleft,bleft: std_logic_vector(7 downto 0); begin acount=numa; bcount=numb; x1:process(en) begin if en=0 then ared=01010101; ayellow=00000101; agreen=01000000; aleft=00010101; bred=01100101; byellow=00000101; bgreen=00110000; bleft=00010101; end if; end process; x2:process(clk,en) begin if clk=1 and clkevent then if en=1 then if tempa=0 then tempanuma=agreen; lampa=0010; stateanuma=ayellow; lampa=0100; stateanuma=aleft; lampa=0001; stateanuma=ayellow; lampa=0100; stateanuma=ared; lampa=1000; statealampa1) then if numa(3 downto 0)=0 then numa(3 downto 0)=1001; numa(7 downto 4)=numa(7 downto 4)-1; else numa(3 downto 0)=numa(3 downto 0)-1; end if; else if numa=1 then tempa=0; numa=numa-1; end if; end if; end if; else lampa=1000; statea=000; tempa=0; end if; end if; end process x2; x3:process(clk,en) begin if clk=1 and clkevent then if en=1 then if tempb=0 then tempbnumb=bred; lampb=1000; statebnumb=bgreen; lampb=0010; statebnumb=byellow; lampb=0100; statebnumb=bleft; lampb=0001; statebnumb=byellow; lampb=0100; stateblampb1) then if numb(3 downto 0)=0 then numb(3 downto 0)=1001; numb(7 downto 4)=numb(7 downto 4)-1; else numb(3 downto 0)=numb(3 downto 0)-1; end if; else if numb=1 then tempb=0; numb=numb-1; end if; end if; end if; else lampb=1000; stateb=000; tempbdisplaydisplaydisplaydisplaydisplaydisplaydisplaydisplaydisplaydisplaydisplay=1110011; end case; end process; end led_arch; library ieee;use ieee.std_logic_1164.all;entity EDA3 is port(cl,sn: in std_logic; lama,lamb: out std_logic_vector(3 downto 0); disp1,disp2,disp3,disp4: out std_logic_vector(6 downto 0);end EDA3;architecture a of EDA3 is signal m,n: std_logic_vector(7 downto 0); component EDA2 port( data: in std_logic_vector(3 downto 0); display: out std_logic_vector(6 downto 0); end component; component EDA1 port(clk,en : in std_logic; lampa,lampb: out std_logic_vector(3 downto 0); acount,bcount: out std_logic_vector(7 downto 0); end component; begin u1 : EDA1 port map(cl,sn,lama,lamb,m,n); u2 : EDA2 port map(m(3 downto 0),disp1);