DS18B20时序.doc

.DS18B20时序Author：exploer CIEE ,CAU 2008-9-16本文档参照Maxim公司DS18B20的Datasheet而完成。其中，加了灰框的部分为原文档内容，其中英文部分为官方文档内容，中文部分为本人的翻译。限于本人水平，本文档可能存在错误或者让人误解的内容，对于因此引起的一切问题作者（exploer，CIEE-CAU）概不负责。INITIALIZATION PROCEDURERESET AND PRESENCE PULSES 初始化序列复位和存在脉冲All communication with the DS18B20 begins with an initialization sequence that consists of a reset pulse from the master followed by a presence pulse from the DS18B20. This is illustrated in Figure 13. When the DS18B20 sends the presence pulse in response to the reset, it is indicating to the master that it is on the bus and ready to operate.DS18B20的所有通信都由由复位脉冲组成的初始化序列开始。该初始化序列由主机发出，后跟由DS18B20发出的存在脉冲（presence pulse）。下图（插图13，即如下截图）阐述了这一点。当发出应答复位脉冲的存在脉冲后，DS18B20通知主机它在总线上并且准备好操作了。During the initialization sequence the bus master transmits (TX) the reset pulse by pulling the 1-Wire bus low for a minimum of 480s. The bus master then releases the bus and goes into receive mode (RX). 在初始化步骤中，总线上的主机通过拉低单总线至少480s来产生复位脉冲。然后总线主机释放总线并进入接收模式。When the bus is released, the 5k pullup resistor pulls the 1-Wire bus high. When the DS18B20 detects this rising edge, it waits 15s to 60s and then transmits a presence pulse by pulling the 1-Wire bus low for 60s to 240s.当总线释放后，5k的上拉电阻把单总线上的电平拉回高电平。当DS18B20检测到上升沿后等待15到60us，然后以拉低总线60-240us的方式发出存在脉冲。如文档所述，主机将总线拉低最短480us，之后释放总线。由于5k上拉电阻的作用，总线恢复到高电平。DS18B20检测到上升沿后等待15到60us，发出存在脉冲：拉低总线60-240us。至此，初始化和存在时序完毕。根据上述要求编写的复位函数为： 首先是延时函数：（由于DS18B20延时均以15us为单位，故编写了延时单位为15us的延时函数，注意：以下延时函数晶振为12MHz）/*函数：Delayxus_DS18B20功能：DS18B20延时函数参数：t为定时时间长度返回：无说明： 延时公式：15n+15 （近似）,晶振12Mhz*/void Delayxus_DS18B20(unsigned int t)for(t;t0;t-)_nop_();_nop_();_nop_();_nop_();_nop_(); _nop_();延时函数反汇编代码（方便分析延时公式）C:0x0031 7F01 MOV R7,#0x01C:0x0033 7E00 MOV R6,#0x00C:0x0035 1206A6 LCALL delayxus(C:06A6) 38: void Delayxus_DS18B20（unsigned int t) 39: 40: for(t;t0;t-) C:0x06A6 D3 SETB CC:0x06A7 EF MOV A,R7C:0x06A8 9400 SUBB A,#0x00C:0x06AA EE MOV A,R6C:0x06AB 9400 SUBB A,#0x00C:0x06AD 400B JC C:06BA 41: 42: _nop_();_nop_();_nop_();_nop_(); C:0x06AF 00 NOP C:0x06B0 00 NOP C:0x06B1 00 NOP C:0x06B2 00 NOP 43: C:0x06B3 EF MOV A,R7C:0x06B4 1F DEC R7C:0x06B5 70EF JNZ Delayxus_DS18B20 (C:06A6)C:0x06B7 1E DEC R6C:0x06B8 80EC SJMP Delayxus_DS18B20 (C:06A6) 44: _nop_(); _nop_(); C:0x06BA 00 NOP C:0x06BB 00 NOP 45: C:0x06BC 22 RET 分析上述反汇编代码，可知延时公式为15*（t+1）/*函数：RST_DS18B20功能：复位DS18B20，读取存在脉冲并返回参数：无返回：1 ：复位成功 ；0：复位失败说明： 拉低总线至少480us ;可用于检测DS18B20工作是否正常*/bit RST_DS18B20()bit ret=1;DQ=0;/* 拉低总线 */Delayxus_DS18B20(32);/* 为保险起见，延时495us */DQ=1;/* 释放总线 ，DS18B20检测到上升沿后会发送存在脉冲*/Delayxus_DS18B20(4);/* 需要等待1560us，这里延时75us后可以保证接受到的是存在脉冲（如果通信正常的话） */ret=DQ;Delayxus_DS18B20(14);/* 延时495us，让ds18b20释放总线，避免影响到下一步的操作 */ DQ=1;/* 释放总线 */return(ret);写时序：READ/WRITE TIME SLOTS 读写时隙The bus master writes data to the DS18B20 during write time slots and reads data from the DS18B20 during read time slots. One bit of data is transmitted over the 1-Wire bus per time slot. 主机在写时隙向DS18B20写入数据，并在读时隙从DS18B20读入数据。在单总线上每个时隙只传送一位数据。WRITE TIME SLOTS 写时间隙There are two types of write time slots: “Write 1” time slots and “Write 0” time slots. The bus master uses a Write 1 time slot to write a logic 1 to the DS18B20 and a Write 0 time slot to write a logic 0 to the DS18B20. All write time slots must be a minimum of 60s in duration with a minimum of a 1s recovery time between individual write slots. Both types of write time slots are initiated by the master pulling the 1-Wire bus low (see Figure 14). 有两种写时隙：写“0”时间隙和写“1”时间隙。总线主机使用写“1”时间隙向DS18B20写入逻辑1，使用写“0”时间隙向DS18B20写入逻辑0.所有的写时隙必须有最少60us的持续时间，相邻两个写时隙必须要有最少1us的恢复时间。两种写时隙都通过主机拉低总线产生（见插图14）。To generate a Write 1 time slot, after pulling the 1-Wire bus low, the bus master must release the 1-Wire bus within 15s. When the bus is released, the 5k pullup resistor will pull the bus high. To generate a Write 0 time slot, after pulling the 1-Wire bus low, the bus master must continue to hold the bus low for the duration of the time slot (at least 60s).为产生写1时隙，在拉低总线后主机必须在15s内释放总线。在总线被释放后，由于5k上拉电阻的作用，总线恢复为高电平。为产生写0时隙，在拉低总线后主机必须继续拉低总线以满足时隙持续时间的要求(至少60s)。The DS18B20 samples the 1-Wire bus during a window that lasts from 15s to 60s after the master initiates the write time slot. If the bus is high during the sampling window, a 1 is written to the DS18B20. If the line is low, a 0 is written to the DS18B20.在主机产生写时隙后，DS18B20会在其后的15到60us的一个时间窗口内采样单总线。在采样的时间窗口内，如果总线为高电平，主机会向DS18B20写入1；如果总线为低电平，主机会向DS18B20写入0。如文档所述，所有的写时隙必须至少有60us的持续时间。相邻两个写时隙必须要有最少1us的恢复时间。所有的写时隙（写0和写1）都由拉低总线产生。为产生写1时隙，在拉低总线后主机必须在15us内释放总线（拉低的电平要持续至少1us）。由于上拉电阻的作用，总线电平恢复为高电平，直到完成写时隙。为产生写0时隙，在拉低总线后主机持续拉低总线即可，直到写时隙完成后释放总线（持续时间60-120us）。写时隙产生后，DS18B20会在产生后的15到60us的时间内采样总线，以此来确定写0还是写1。满足上述要求的写函数为：/*函数：WR_Bit功能：向DS18B20写一位数据参数：i为待写的位返回：无说明： 总线从高拉到低产生写时序*/void WR_Bit(bit i)DQ=0;/产生写时序 _nop_();_nop_();/总线拉低持续时间要大于1us DQ=i;/写数据 ，0 和1均可Delayxus_DS18B20(3);/延时60us，等待ds18b20采样读取 DQ=1;/释放总线 /* 函数：WR_Byte功能：DS18B20写字节函数，先写最低位参数：dat为待写的字节数据返回：无说明：无*/void WR_Byte(unsigned char dat)unsigned char i=0;while(i+=1;/注意不要写成dat1读时序：READ TIME SLOTS 读时间隙The DS18B20 can only transmit data to the master when the master issues read time slots. Therefore, the master must generate read time slots immediately after issuing a Read Scratchpad BEh or Read Power Supply B4h command, so that the DS18B20 can provide the requested data. In addition, the master can generate read time slots after issuing Convert T 44h or Recall E 2B8h commands to find out the status of the operation as explained in the DS18B20 Function Commands section. DS18B20只有在主机发出读时隙后才会向主机发送数据。因此，在发出读暂存器命令 BEh或读电源命令B4h后，主机必须立即产生读时隙以便DS18B20提供所需数据。另外，主机可在发出温度转换命令T 44h或Recall命令E 2B8h 后产生读时隙，以便了解操作的状态(在 DS18B20操作指令 这一节会详细解释)。All read time slots must be a minimum of 60s in duration with a minimum of a 1s recovery time between slots. A read time slot is initiated by the master device pulling the 1-Wire bus low for a minimum of 1s and then releasing the bus (see Figure 14). After the master initiates the read time slot, the DS18B20 will begin transmitting a 1 or 0 on bus. The DS18B20 transmits a 1 by leaving the bus high and transmits a 0 by pulling the bus low. When transmitting a 0, the DS18B20 will release the bus by the end of the time slot, and the bus will be pulled back to its high idle state by the pullup resister. Output data from the DS18B20 is valid for 15s after the falling edge that initiated the read time slot. Therefore, the master must release the bus and then sample the bus state within 15s from the start of the slot. 所有的读时隙必须至少有60us的持续时间。相邻两个读时隙必须要有最少1us的恢复时间。所有的读时隙都由拉低总线，持续至少1us后再释放总线（由于上拉电阻的作用，总线恢复为高电平）产生。在主机产生读时隙后，DS18B20开始发送0或1到总线上。DS18B20让总线保持高电平的方式发送1，以拉低总线的方式表示发送0.当发送0的时候，DS18B20在读时隙的末期将会释放总线，总线将会被上拉电阻拉回高电平（也是总线空闲的状态）。DS18B20输出的数据在下降沿（下降沿产生读时隙）产生后15us后有效。因此，主机释放总线和采样总线等动作要在15s内完成。Figure 15 illustrates that the sum of TINIT, TRC, and TSAMPLE must be less than 15s for a read time slot. 插图15表明了对于读时隙，TINIT（下降沿后低电平持续时间）, TRC（上升沿）和TSAMPLE（主机采样总线）的时间和要在15s以内。Figure 16 shows that system timing margin is maximized by keeping TINIT and TRC as short as possible and by locating the master sample time during read time slots towards the end of the 15s period.插图16显示了最大化系统时间宽限的方法：让TINIT 和TRC尽可能的短，把主机采样总线放到15s这一时间段的尾部。由文档可知，DS18B20只有在主机发出读时隙时才能发送数据到主机。因此，主机必须在BE 命令，B4命令后立即产生读时隙以使DS18B20提供相应的数据。另外，在44命令，B8命令后也要产生读时隙。所有的读时隙必须至少有60us的持续时间。相邻两个读时隙必须要有最少1us的恢复时间。所有的读时隙都由拉低总线，持续至少1us后再释放总线（由于上拉电阻的作用，总线恢复为高电平）产生。DS18B20输出的数据在下降沿产生后15us后有效。因此，释放总线和主机采样总线等动作要在15us内完成。满足以上要求的函数为：/* 函数：Read_Bit功能：向DS18B20读一位数据参数：无返回：bi