EDA课程设计电子钟.doc

EDA课程设计-电子钟 一、设计要求1、基本功能要求：设计一个电子时钟，要求可以显示时、分、秒，用户可以设置时间。扩展功能要求：2、 跑表功能，闹钟功能，调整数码管的亮度。二、系统结构控制键jian5、jian4、jian7、jian8：数码管显示段选信号输出sg：选择6位数码管中的某一个显示数据；发光二极管控制信号输出led（70）闹钟声音输出speaker通过一个10M信号分出各种所需频率功能介绍 运行后，选择模式7，8位数码管分显示时间的时、分、秒，当前为模式0：时间显示模式，按键7为模式选择键，按下按键7，系统进入模式1，第二次按下为模式2，设置时间模式，第三次按下为跑表模式，第四次为闹钟设置模式，第五次为亮度调节模式：设置时间模式，按键4控制更改数码管的位，按键5控制选中数码管的数值，时间设置完成后，按键按键8，设置时间会保存住，并在模式0中显示；系统进入模式2：秒表模式，按键4为开始/结束键，按键5为清零键；系统进入模式3：闹钟设置模式，相关设置与模式1相同，当当前时间与闹钟设置时间相同时，喇叭就会响；系统进入模式4:亮度调节模式，通过按键4设置亮度，共三种亮度；再按下按键7，系统又会进入模式0。4、RTL图三、VHDL源程序1、library ieee; -通过10M分出所需频率use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fenpin isport (clk_10M : in std_logic;clk_10000 : out std_logic;clk_100 : out std_logic;clk_1 : out std_logic);end entity;architecture sub1 of fenpin issignal Q_1 : std_logic_vector(8 downto 0);signal Q_2 : std_logic_vector(6 downto 0);signal Q_3 : std_logic_vector(6 downto 0);signal clk10000 : std_logic;signal clk100 : std_logic;signal clk1 : std_logic;beginprocess(clk_10M)beginif clk_10Mevent and clk_10M=1 thenif Q_1=500 thenQ_1 = 000000000;clk10000 = not clk10000;if Q_2=100 then Q_2 = 0000000;clk100= not clk100;if Q_3=100 then Q_3 = 0000000;clk1=not clk1;else Q_3=Q_3+1;end if;else Q_2=Q_2+1;end if;else Q_1=Q_1+1;end if;end if;end process;clk_10000 = clk10000;clk_100 = clk100;clk_1 bt11= 0000000&(light);a bt11= 000000&(light)&0;a bt11= 00000&(light)&00;a bt11= 0000&(light)&000;a bt11= 000&(light)&0000;a bt11= 00&(light)&00000;a bt11= 0&(light)&000000;a bt11= (light)&0000000;a null; end case; end process p1;p2:process(clk_10000) begin if clk_10000event and clk_10000 =1 then cnt8 sg11 sg11 sg11 sg11 sg11 sg11 sg11 sg11 sg11 sg11 sg11 sg11 sg11 sg11 sg11 sg11 null; end case; end process p3; process(jian4,moshi)begin if moshi=4 thenif jian4event and jian4=1 thenif flash =2 then flash=0; else flash light if count1=2 then count1=0; light=1;else count1=count1+1;light if count2=4 then count2=0; light=1;else count2=count2+1;light=0;end if;end case;end if;end process;end;3、library ieee; -跑表开始暂停use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity paobiao isport(clk_1:in std_logic; jian8:in std_logic; shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9; shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:out integer range 0 to 9);end entity;architecture bhv of paobiao issignal shi:integer range 0 to 100;signal fen:integer range 0 to 100;signal miao:integer range 0 to 100;begin process(clk_1,jian8,shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1) beginif jian8=1 thenshi=shishi1*10+shige1;fen=fenshi1*10+fenge1;miao=miaoshi1*10+miaoge1; elsif clk_1event and clk_1=1 then if miao=59 then miao=0; fen59 then fen=0; shi23 then shi=0; else miao=miao+1; end if;end if;end process;miaoge2=miao rem 10;miaoshi2=miao/10;fenge2=fen rem 10;fenshi2=fen/10;shige2=shi rem 10;shishi2=shi/10;end;4、library ieee; -设置当前时间use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity settime isport(moshi:in integer range 0 to 4; jian4,jian5:in std_logic; shishi,shige,fenshi,fenge,miaoshi,miaoge:out integer range 0 to 9);end entity;architecture bav of settime issignal a:integer range 0 to 5;signal shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1: integer range 0 to 9; begin process(moshi,jian4)beginif moshi=1 then if jian4event and jian4=1 thenif a 5 thena=a+1;else a=0;end if;end if;end if;end process;process(moshi,a,jian5)beginif moshi=1 thenif a=0 thenif jian5event and jian5=1 thenif miaoge1 =9 thenmiaoge1=0;else miaoge1=miaoge1+1;end if; end if;end if;if a=1 then if jian5event and jian5=1 thenif miaoshi1 =5 thenmiaoshi1=0;else miaoshi1=miaoshi1+1;end if; end if;end if;if a=2 then if jian5event and jian5=1 thenif fenge1 =9 thenfenge1=0;else fenge1=fenge1+1;end if; end if;end if;if a=3 then if jian5event and jian5=1 thenif fenshi1 =5 thenfenshi1=0;else fenshi1=fenshi1+1;end if; end if;end if;if a=4 then if jian5event and jian5=1 thenif shige1 =9 thenshige1=0;else shige1=shige1+1;end if; end if;end if;if a=5 then if jian5event and jian5=1 thenif shishi1 =2 thenshishi1=0;else shishi1=shishi1+1;end if; end if;end if;end if;end process; miaoge=miaoge1;miaoshi=miaoshi1;fenge=fenge1;fenshi=fenshi1;shige=shige1;shishi=shishi1;end;5、library ieee; -秒表功能use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity miaobiao isport(clk_100:in std_logic; moshi:in integer range 0 to 4; jian5,jian4:in std_logic; fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:out integer range 0 to 9);end entity;architecture bhv of miaobiao issignal fen,miao,xmiao:integer range 0 to 99;signal start:std_logic:=0;signal reset:std_logic:=0;beginprocess(clk_100,jian5,jian4,moshi,reset,start) beginif moshi=2 thenif reset=1 then fen=0;miao=0;xmiao=0;elsif start=1 then elsif clk_100event and clk_100=1 then if xmiao=99 then xmiao=0; miao59 then miao=0; fen23 then fen=0; else xmiao=xmiao+1;end if; end if;end if;end process;process(jian4,start)beginif jian4event and jian4=1 then start=not start;else start=start;end if;end process; process(jian5,reset)beginif jian5event and jian5=1 then reset=not reset;else reset= reset;end if;end process; xmiaoge=xmiao rem 10;xmiaoshi=xmiao/10;miaoge=miao rem 10;miaoshi=miao/10;fenge=fen rem 10;fenshi=fen/10;end;6、library ieee; -设置闹钟时间use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity naozhongset isport(moshi:in integer range 0 to 4; jian4,jian5:in std_logic; shishi,shige,fenshi,fenge,miaoshi,miaoge:out integer range 0 to 9);end entity;architecture bav of naozhongset issignal a:integer range 0 to 5;signal fenshi1,fenge1,miaoge1: integer range 0 to 9;signal shishi1: integer range 0 to 9:=1;signal shige1: integer range 0 to 9:=2;signal miaoshi1: integer range 0 to 9:=0;begin process(moshi,jian4)beginif moshi=3 then if jian4event and jian4=1 thenif a 5 thena=a+1;else a=0;end if;end if;end if;end process;process(moshi,a,jian5)beginif moshi=3 thenif a=0 thenif jian5event and jian5=1 thenif miaoge1 =9 thenmiaoge1=0;else miaoge1=miaoge1+1;end if; end if;end if;if a=1 then if jian5event and jian5=1 thenif miaoshi1 =5 thenmiaoshi1=0;else miaoshi1=miaoshi1+1;end if; end if;end if;if a=2 then if jian5event and jian5=1 thenif fenge1 =9 thenfenge1=0;else fenge1=fenge1+1;end if; end if;end if;if a=3 then if jian5event and jian5=1 thenif fenshi1 =5 thenfenshi1=0;else fenshi1=fenshi1+1;end if; end if;end if;if a=4 then if jian5event and jian5=1 thenif shige1 =9 thenshige1=0;else shige1=shige1+1;end if; end if;end if;if a=5 then if jian5event and jian5=1 thenif shishi1 =2 thenshishi1=0;else shishi1=shishi1+1;end if; end if;end if;end if;end process; miaoge=miaoge1;miaoshi=miaoshi1;fenge=fenge1;fenshi=fenshi1;shige=shige1;shishi=shishi1;end;7、library ieee; -闹钟喇叭输出use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity naozhongspeaker isport(clk_100:in std_logic; shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9; shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:in integer range 0 to 9; speaker:out std_logic);end entity;architecture bav of naozhongspeaker isbegin process(clk_100, shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1, shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2) beginif shishi2=shishi1 and shige2=shige1 and fenshi2=fenshi1 and fenge2=fenge1 and miaoshi2=miaoshi1 thenspeaker=clk_100;else speaker=1;end if;end process;end;8、library ieee; -转换模式use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity moshi is port(jian7:in std_logic; moshi:out integer range 0 to 4);end;architecture one of moshi is signal moshis:integer range 0 to 4; begin process(jian7) begin if jian7event and jian7=1 then if moshis=4 then moshis=0; else moshis=moshis+1; end if; end if; end process;moshi a0=shishi1;a1=shige1;a3=fenshi1;a4=fenge1;a6=miaoshi1;a7 a0=shishi2;a1=shige2;a3=fenshi2;a4=fenge2;a6=miaoshi2;a7 a0=fenshi;a1=fenge;a3=miaoshi;a4=miaoge;a6=xmiaoshi;a7 a0=shishi3;a1=shige3;a3=fenshi3;a4=fenge3;a6=miaoshi3;a7 a0=8;a1=8;a3=8;a4=8;a6=8;a7clk_1s, jian8=jian8,shishi1=shishi2s,shige1=shige2s,fenshi1=fenshi2s,fenge1=fenge2s,miaoshi1=miaoshi2s,miaoge1=miaoge2s, shishi2=shishi1s,shige2=shige1s,fenshi2=fenshi1s,fenge2=fenge1s,miaoshi2=miaoshi1s,miaoge2=miaoge1s);u2:xianshi port map(clk_10000=clk_10000s,jian4=jian4,moshi=moshis,a0=a0s,a1=a1s,a3=a3s,a4=a4s,a6=a6s,a7=a7s,sg11=sg,bt11=bt);u3:settime port map(moshi=moshis,jian5=jian5,jian4=jian4, shishi=shishi2s,shige=shige2s,fenshi=fenshi2s,fenge=fenge2s,miaoshi=miaoshi2s,miaoge=miaoge2s);u4:moshi port map(jian7=jian7, moshi=moshis);u5:mux5_1 port map(moshi=moshis, shishi1=shishi1s,shige1=shige1s,fenshi1=fenshi1s,fenge1=fenge1s,miaoshi1=miaoshi1s,miaoge1=miaoge1s, shishi2=shishi2s,shige2=shige2s,fenshi2=fenshi2s,fenge2=fenge2s,mia