简易电子时钟设计 verilog FPGA.doc

实验七、简易电子时钟设计一、简易电子时钟设计实验程序：moduleclock(clk,clr,minute_h,minute_l,second_h,second_l);inputclk;inputclr;output3:0minute_h;/分钟的高位output3:0minute_l;/分钟的低位output3:0second_h;/秒钟的高位output3:0second_l;/秒钟的低位reg3:0minute_h;reg3:0minute_l;reg3:0second_h;reg3:0second_l;regsecond_l_flag;/秒钟低位的进位标志regsecond_h_flag;/秒钟高位的进位标志regminute_l_flag;/分钟低位的进位标志regminute_h_flag;/分钟高位的进位标志regclk1;/实验时选为2hz的时钟频率always(posedgeclkornegedgeclr)beginif(!clr)clk1=1b0;elseclk1=clk1;end/秒钟的低位always(posedgeclk1or negedgeclr)if(!clr)beginsecond_l=4b0000;second_l_flag=1b0;endelseif(second_l=4b1000)beginsecond_l=second_l+1b1;second_l_flag=1b1;endelseif(second_l4b1000)begin second_l=second_l+1b1;second_l_flag=1b0;endelsebeginsecond_l=4b0000;second_l_flag=1b0;end /秒钟的高位always(negedgesecond_l_flagornegedgeclr)if(!clr)beginsecond_h=4b0000;second_h_flag=1b0;endelseif(second_h=4b0100)beginsecond_h=second_h+1b1;second_h_flag=1b1;endelseif(second_h4b0100)beginsecond_h=second_h+1b1;second_h_flag=1b0;endelsebeginsecond_h=4b0000;second_h_flag=1b0;end/分钟的低位always(negedgesecond_h_flagor negedgeclr)if(!clr)beginminute_l=4b0000;minute_l_flag=1b0;endelseif(minute_l=4b1000)beginminute_l=minute_l+1b1;minute_l_flag=1b1;endelseif(minute_l4b1000)beginminute_l=minute_l+1b1;minute_l_flag=1b0;endelsebeginminute_l=4b0000;minute_l_flag=1b0;end/分钟的高位always(negedgeminute_l_flagornegedgeclr)if(!clr)beginminute_h=4b0000;minute_h_flag=1b0;endelseif(minute_h=4b0100)beginminute_h=minute_h+1b1;minute_h_flag=1b1;endelseif(minute_h4b0100)beginminute_h=minute_h+1b1;minute_h_flag=1b0;endelsebeginminute_h=4b0000;minute_h_flag=1b0;endendmodule二、简易电子时钟设计测试程序：timescale10ns/1nsmoduleclock_test;regclk_test;regclr_test;wire3:0minute_h_test;wire3:0minute_l_test;wire3:0second_h_test;wire3:0second_l_test;clockclock1(.clk(clk_test), .clr(clr_test), .minute_h(minute_h_test), .minute_l(minute_l_test), .second_h(second_h_test), .second_l(second_l_test);initialbegin#0clk_test=1b0;clr_test=1b1;#10