如何使用Debussy与ModelSim做Co-Simulation (SOC) (Verilog) (VHDL) (Debussy) (ModelSim)

如何使用Debussy與ModelSim做Co-Simulation? (SOC) (Verilog) (VHDL) (Debussy) (ModelSim)Abstract本文介紹如何使用Debussy與ModelSim做Co-Simulation，並使用Verilog、VHDL以及Verilog搭配VHDL交叉一起simulation。Introduction使用環境：Debussy 5.4 v9 + ModelSim SE 6.3e我之前一直使用Debussy + NC-Verilog做simulation，Debussy (Verdi)可以說是HDL的Source Insight，是trace與debug的神兵利器，NC-Verilog也是Verilog simulator中速度最快的，可是最近因工作需要，拿到的一包code卻是用Verilog寫RTL，用VHDL寫testbench，所以必須2種語言一起做simulation，我在NC-Verilog一直無法成功讓兩種語言一起simulation。ModelSim雖然支援Verilog + VHDL co-simulation，但用慣Debussy的我還是無法忘懷其方便的trace code方式，所以若能讓ModelSim也能dump出Debussy所需要的fsdb檔案，這樣就太完美了。接下來會分4個方式討論1.RTL與testbench皆使用Verilog2.RTL與testbench皆使用VHDL3.RTL使用VHDL，testbench使用Verilog4.RTL使用Verilog，testbench使用VHDL1.RTL與testbench皆使用VerilogStep 1：設定ModeSim使用Verilog PLI (因為testbench使用Verilog)將C:NovasDebussysharePLImodelsim_pliWINNTnovas.dll複製到C:Modeltech_6.3ewin32下修改C:Modeltech_6.3emodelsim.ini，將Veriuser部分修改成如下所示：; List of dynamically loaded objects for Verilog PLI applications; Veriuser = veriuser.sl; use by verilogVeriuser = novas.dll; use by vhdl; Veriuser = novas_fli.dll复制代码modelsim.ini是個read only檔，要修改前記得修改其屬性才能存檔。Step 2：RTL部分 (以4 bit counter為例)counter.v / Verilog 1 /* 2 (C) OOMusou 2011 3 4 Filename : counter.v 5 Simulator : ModelSim 6.3e, Debussy 5.4 v9 6 Description : ModelSim with debussy 7 Release : 01/31/2010 1.0 8 */ 9 10 module counter (11 clk,12 rst_n,13 cnt14 );15 16 input clk;17 input rst_n;18 output 3:0 cnt;19 20 reg 3:0 cnt;21 22 always(posedge clk, negedge rst_n) begin23 if (rst_n) 24 cnt = 4h0;25 else26 cnt vsim -c -do sim.do Reading C:/Modeltech_6.3e/tcl/vsim/pref.tcl # 6.3e# do sim.do # * Warning: (vlib-34) Library already exists at work.# Model Technology ModelSim SE vlog 6.3e Compiler 2008.02 Feb 2 2008# - Compiling module counter# # Top level modules:# counter# Model Technology ModelSim SE vlog 6.3e Compiler 2008.02 Feb 2 2008# - Compiling module counter_tb# # Top level modules:# counter_tb# vsim counter_tb # * Note: (vsim-3813) Design is being optimized due to module recompilation.# * Note: (vsim-3865) Due to PLI being present, full design access is being specified.# Loading C:Modeltech_6.3ewin32/novas.dll# / ModelSim SE 6.3e Feb 2 2008 # /# / Copyright 1991-2008 Mentor Graphics Corporation# / All Rights Reserved.# /# / THIS WORK CONTAINS TRADE SECRET AND # / PROPRIETARY INFORMATION WHICH IS THE PROPERTY# / OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS# / AND IS SUBJECT TO LICENSE TERMS.# /# Loading work.counter_tb(fast)# Loading work.counter(fast)# Novas FSDB Dumper for ModelSim, Release 5.4v9 (Win95/NT) 05/04/2005# Copyright (C) 1996 - 2004 by Novas Software, Inc.# *Novas* Create FSDB file counter.fsdb# *Novas* Start dumping the scope(counter_tb), layer(0).# *Novas* End of dumping.# * Note: $finish : counter_tb.v(27)# Time: 200 ns Iteration: 0 Instance: /counter_tb复制代码Step 6：執行Debussy批次檔部份deb.batdebussy -2001 counter_tb.v counter.v -ssf counter.fsdb -sswr counter.rc-2001表示支援Verilog 2001語法-ssf 載入Debussy dump file-sswr 載入Debussy signal file 執行結果 2.RTL與testbench皆使用VHDLStep 1：設定ModelSim使用VHDL FLI (因為testbench使用VHDL)將C:NovasDebussysharePLImodelsim_fli54WINNTnovas_fli.dll複製到C:Modeltech_6.3ewin32下修改C:Modeltech_6.3emodelsim.ini，將Veriuser部分修改成如下所示： ; List of dynamically loaded objects for Verilog PLI applications; Veriuser = veriuser.sl; use by verilog;Veriuser = novas.dll; use by vhdlVeriuser = novas_fli.dll复制代码modelsim.ini是個read only檔，要修改前記得修改其屬性才能存檔。複製C:NovasDebussysharePLImodelsim_fli54WINNTnovas.vhd到自己的project底下(為什麼Verilog不需要這個檔，而VHDL需要這個檔，稍後會解釋) Step 2：RTL部分 (以4 bit counter為例)counter.vhd / VHDL 1 - (C) OOMusou 2011 2 3 - Filename : counter.vhd 4 - Simulator : ModelSim 6.3e, Debussy 5.4 v9 5 - Description : ModelSim with debussy 6 - Release : 02/05/2011 1.0 7 8 library IEEE; 9 use IEEE.std_logic_1164.all;10 use IEEE.std_logic_unsigned.all;11 12 entity counter is13 port ( clk : in std_logic;14 rst_n : in std_logic;15 cnt : out std_logic_vector(3 downto 0);16 end entity counter;17 18 architecture arc of counter is19 signal cnt_r : std_logic_vector(3 downto 0);20 begin21 process(clk, rst_n) 22 begin23 if (rst_n = 0) then24 cnt_r = 0000;25 elsif rising_edge(clk) then26 cnt_r = cnt_r + 1;27 end if;28 end process;29 30 cnt = cnt_r;31 end arc;复制代码Step 3：Testbench部分counter.vhd / VHDL 1 - (C) OOMusou 2011 2 3 - Filename : counter_tb.vhd 4 - Simulator : ModelSim 6.3e, Debussy 5.4 v9 5 - Description : ModelSim with debussy 6 - Release : 01/31/2010 1.0 7 8 library IEEE; 9 use IEEE.std_logic_1164.all;10 use IEEE.std_logic_unsigned.all;11 use work.pkg.all;12 13 entity counter_tb is 14 end entity counter_tb;15 16 architecture arc of counter_tb is17 component counter 18 port (19 clk : in std_logic;20 rst_n : in std_logic;21 cnt : out std_logic_vector(3 downto 0)22 );23 end component;24 25 signal clk : std_logic := 0;26 signal rst_n : std_logic := 0;27 signal cnt : std_logic_vector(3 downto 0);28 29 begin30 process31 begin - 50MHz32 clk_loop : loop33 clk = 0;34 wait for 10 ns;35 clk = 1;36 wait for 10 ns;37 end loop clk_loop;38 end process;39 40 process41 begin42 wait for 5 ns;43 rst_n clk,56 rst_n = rst_n,57 cnt = cnt58 );59 end arc;复制代码11行 use work.pkg.all;這是因為novas.vhd與VHDL FLI的原因，稍後會解釋。47行processbegin fsdbDumpfile(counter.fsdb); fsdbDumpvars(0, counter_tb); wait;end process;复制代码一樣使用fsdbDumpfile()與fsdbDumpvars()兩個Debussy所提供的函數，不過在VHDL FLI並不需要如Verilog PLI一樣加上$。wait也一定要加上，否則在ModelSim做simulation時會造成無窮回圈無法停止。Step 4：ModelSim script部分vsim.dovlib workvcom novas.vhdvcom counter.vhdvcom counter_tb.vhdvsim counter_tbrun 200nsq复制代码因為是VHDL，所以全部改用vcom編譯。其中novas.vhd是從Debussy目錄複製過來的，為什麼需要編譯這個檔案呢?VHDL FLI (Foreign Language Interface)與Verilog PLI (Programming Language Interface)不同的地方在於，當你自己提供由C寫的function給simulator使用時，Verilog PLI會自己到所提供的dll去找是否有此function，但VHDL FLI需要自己去提供mapping的動作，告訴simulator哪一個function對應dll內那個function，novas.vhd就是提供這個mapping的腳色。 若直接使用Debussy所提供的novas.vhd，在執行ModelSim會有以下錯誤訊息。# * Warning: (vsim-FLI-3159) Failed to find foreign function fliparseVariableInFile in FLI object file C:Modeltech_6.3ewin32/./novas_fli.dll.复制代码意思是novas.vhd定義的fliparseVariableInFile在novas_fli.dll找不到，致於為什麼會有此錯誤，我並不清楚。將novas.vhd修改成如下所示：novas.vhd / VHDL 1 package pkg is 2 attribute foreign : string; 3 4 procedure fsdbDumpfile (file_name : in string); 5 attribute foreign of fsdbDumpfile : procedure is fliparseTraceInit ./novas_fli.dll; 6 7 procedure fsdbDumpvars (depth : in integer; 8 region_name : in string); 9 attribute foreign of fsdbDumpvars : procedure is fliparsePartial ./novas_fli.dll;10 end;11 12 package body pkg is 13 procedure fsdbDumpfile(file_name : in string) is14 begin15 assert false report ERROR : foreign subprogram not called severity note;16 end;17 18 procedure fsdbDumpvars(depth : in integer;19 region_name : in string) is20 begin21 assert false report ERROR : foreign subprogram not called severity note;22 end;23 end; 24 25 entity novas is end; 26 27 architecture novas_arch of novas is28 attribute foreign : string;29 attribute foreign of novas_arch : architecture is fliparseCommand novas_fli.dll;30 begin31 end;32 复制代码也就是僅留下fsdbDumpfile()與fsdbDumpvars()兩個function，其他的都刪除。根據我使用Debussy的經驗，只要留這兩個function就夠用了，其他Debussy的function我還真的沒用過。在novas.vhd也看到了這些是定義在pkg這個package下，所以在counter_tb.vhd必須use work.pkg.all。Step 5：執行ModelSim的批次檔mod.batvsim -c -do sim.do執行結果D:0ClareVerilogLabModelSimcounter_vhdlvsim -c -do sim.do Reading C:/Modeltech_6.3e/tcl/vsim/pref.tcl # 6.3e# do sim.do # * Warning: (vlib-34) Library already exists at work.# Model Technology ModelSim SE vcom 6.3e Compiler 2008.02 Feb 2 2008# - Loading package standard# - Compiling package pkg# - Compiling package body pkg# - Loading package pkg# - Compiling entity novas# - Compiling architecture novas_arch of novas# Model Technology ModelSim SE vcom 6.3e Compiler 2008.02 Feb 2 2008# - Loading package standard# - Loading package std_logic_1164# - Loading package std_logic_arith# - Loading package std_logic_unsigned# - Compiling entity counter# - Compiling architecture arc of counter# Model Technology ModelSim SE vcom 6.3e Compiler 2008.02 Feb 2 2008# - Loading package standard# - Loading package std_logic_1164# - Loading package std_logic_arith# - Loading package std_logic_unsigned# - Loading package pkg# - Compiling entity counter_tb# - Compiling architecture arc of counter_tb# vsim counter_tb # Loading C:Modeltech_6.3ewin32/novas.dll# / ModelSim SE 6.3e Feb 2 2008 # /# / Copyright 1991-2008 Mentor Graphics Corporation# / All Rights Reserved.# /# / THIS WORK CONTAINS TRADE SECRET AND # / PROPRIETARY INFORMATION WHICH IS THE PROPERTY# / OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS# / AND IS SUBJECT TO LICENSE TERMS.# /# Loading std.standard# Loading ieee.std_logic_1164(body)# Loading ieee.std_logic_arith(body)# Loading ieee.std_logic_unsigned(body)# Loading work.pkg(body)# Loading C:Modeltech_6.3ewin32/./novas_fli.dll# Loading work.counter_tb(arc)# Loading work.counter(arc)# Novas FSDB Dumper for ModelSim 5.4 (FLI), Release 5.4v9 (Win95/NT) 05/04/2005# Copyright (C) 1996 - 2004 by Novas Software, Inc.# *Novas* Create FSDB file counter.fsdb复制代码Step 6：執行Debussy批次檔部份deb.batdebussy vhdl 93 novas.vhd counter_tb.vhd counter.vhd top counter_tb -ssf counter.fsdb -sswr counter.rc复制代码-vhdl 表示支援VHDL語法，因為Debussy預設支援Verilog-93 表示支援VHDL 93的語法-top 指定top module，在Verilog可以不指定top，Debussy可以自動判斷而抓到top module，但是VHDL沒辦法，需要自己指定，若不指定，待會會有GUI要你手動挑選top module執行結果 3.RTL使用VHDL，testbench使用VerilogStep 1：設定ModeSim使用Verilog PLI (因為testbench使用Verilog)將C:NovasDebussysharePLImodelsim_pliWINNTnovas.dll複製到C:Modeltech_6.3ewin32下修改C:Modeltech_6.3emodelsim.ini，將Veriuser部分修改成如下所示：; List of dynamically loaded objects for Verilog PLI applications; Veriuser = veriuser.sl; use by verilogVeriuser = novas.dll; use by vhdl; Veriuser = novas_fli.dll复制代码modelsim.ini是個read only檔，要修改前記得修改其屬性才能存檔。Step 2：RTL部分 (以4 bit counter為例)counter.vhd / VHDL 1 - (C) OOMusou 2011 2 3 - Filename : counter.vhd 4 - Simulator : ModelSim 6.3e, Debussy 5.4 v9 5 - Description : ModelSim with debussy 6 - Release : 02/05/2011 1.0 7 8 library IEEE; 9 use IEEE.std_logic_1164.all;10 use IEEE.std_logic_unsigned.all;11 12 entity counter is13 port ( clk : in std_logic;14 rst_n : in std_logic;15 cnt : out std_logic_vector(3 downto 0);16 end entity counter;17 18 architecture arc of counter is19 signal cnt_r : std_logic_vector(3 downto 0);20 begin21 process(clk, rst_n) 22 begin23 if (rst_n = 0) then24 cnt_r = 0000;25 elsif rising_edge(clk) then26 cnt_r = cnt_r + 1;27 end if;28 end process;29 30 cnt vsim -c -do sim.do Reading C:/Modeltech_6.3e/tcl/vsim/pref.tcl # 6.3e# do sim.do # * Warning: (vlib-34) Library already exists at work.# Model Technology ModelSim SE vcom 6.3e Compiler 2008.02 Feb 2 2008# - Loading package standard# - Loading package std_logic_1164# - Loading package std_logic_arith# - Loading package std_logic_unsigned# - Compiling entity counter# - Compiling architecture arc of counter# Model Technology ModelSim SE vlog 6.3e Compiler 2008.02 Feb 2 2008# - Compiling module counter_tb# # Top level modules:# counter_tb# vsim counter_tb # Loading C:Modeltech_6.3ewin32/novas.dll# / ModelSim SE 6.3e Feb 2 2008 # /# / Copyright 1991-2008 Mentor Graphics Corporation# / All Rights Reserved.# /# / THIS WORK CONTAINS TRADE SECRET AND # / PROPRIETARY INFORMATION WHICH IS THE PROPERTY# / OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS# / AND IS SUBJECT TO LICENSE TERMS.# /# Loading work.counter_tb(fast)# Loading std.standard# Loading ieee.std_logic_1164(body)# Loading ieee.std_logic_arith(body)# Loading ieee.std_logic_unsigned(body)# Loading work.counter(arc)# Novas FSDB Dumper for ModelSim, Release 5.4v9 (Win95/NT) 05/04/2005# Copyright (C) 1996 - 2004 by Novas Software, Inc.# *Novas* Create FSDB file counter.fsdb# *Novas* Start dumping the scope(counter_tb), layer(0).# * Warning: Unknown scope type: counter_tb.u_counter 1010# : counter_tb.v(30)# Time: 0 ns Iteration: 0 Instance: /counter_tb# * Warning: Unknown scope type: counter_tb.u_counter 1010# : counter_tb.v(30)# Time: 0 ns Iteration: 0 Instance: /counter_tb# *Novas* End of dumping.D:0ClareVerilogLabModelSimcounter_vhdl_verilogvsim -c -do sim.do Reading C:/Modeltech_6.3e/tcl/vsim/pref.tcl # 6.3e# do sim.do # * Warning: (vlib-34) Library already exists at work.# Model Technology ModelSim SE vcom 6.3e Compiler 2008.02 Feb 2 2008# - Loading package standard# - Loading package std_logic_1164# - Loading package std_logic_arith# - Loading package std_logic_unsigned# - Compiling entity counter# - Compiling architecture arc of counter# Model Technology ModelSim SE vlog 6.3e Compiler 2008.02 Feb 2 2008# - Compiling module counter_tb# # Top level modules:# counter_tb# vsim counter_tb # * Note: (vsim-3813) Design is being optimized due to module recompilation.# * Note: (vsim-3865) Due to PLI being present, full design access is being specified.# Loading C:Modeltech_6.3ewin32/novas.dll# / ModelSim SE 6.3e Feb 2 2008 # /# / Copyright 1991-2008 Mentor Graphics Corporation# / All Rights Reserved.# /# / THIS WORK CONTAINS TRADE SECRET AND # / PR