EDA源程序与仿真波形.doc

十六位加法器源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY adder IS PORT ( A:IN STD_LOGIC_VECTOR(15 DOWNTO 0); B:IN STD_LOGIC_VECTOR(15 DOWNTO 0); C:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);END adder;ARCHITECTURE X OF adder ISBEGIN C=A+B;END X;十六位加法器仿真波形：四位的二选一多路选择器源程：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX4 IS PORT ( A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); SEL:IN BIT; Y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END MUX4;ARCHITECTURE Z OF MUX4 ISBEGIN PROCESS(A,B,SEL) BEGIN IF SEL=0 THEN Y=A; ELSE YA=1;B=1;C=1;D=1;E=1;F=1;GA=0;B=1;C=1;D=0;E=0;F=0;GA=1;B=1;C=0;D=1;E=1;F=0;GA=1;B=1;C=1;D=1;E=0;F=0;GA=1;B=0;C=0;D=1;E=1;F=1;G=8 THEN result(i)=0;ELSIF i=7 THEN result(i)=12)OR(i=3) THEN result(i)=4)AND(i=11) THEN result(i)=im(i-4);END IF;END LOOP;ELSIF cnt=10 THENFOR i IN 0 TO 15 LOOPIF i=7 THEN result(i)=8 THEN result(i)=im(i-8);END IF;END LOOP;END IF;END PROCESS;END behave;八位到十六位移位器仿真波形：十六位同步寄存器源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY reg ISPORT(CLK,CLR,CLKEN:IN STD_LOGIC; IN_REG:IN STD_LOGIC_VECTOR(15 DOWNTO 0); OUT_REG:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);END reg;ARCHITECTURE behave OF reg ISBEGINPROCESS(CLK)BEGINIF(CLKEVENT AND CLK=1) THENIF (CLR=1)AND(CLKEN=0) THENOUT_REG(15 DOWNTO 0)=IN_REG(15 DOWNTO 0);ELSIF CLR=0 THENOUT_REG=0000000000000000;END IF;END IF;END PROCESS;END behave;十六位同步寄存器仿真波形：二位异步计数器源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_UNSIGNED.ALl;USE IEEE.STD_LOGIC_1164.ALL;ENTITY COUNTER ISPORT(CLK,CLR:IN STD_LOGIC; SUM:BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0);END COUNTER;ARCHITECTURE behave OF COUNTER IS BEGINPROCESS(CLK)BEGINIF(CLKEVENT AND CLK=1) THENIF CLR=0 THENSUM=00;ELSIF CLR=1 THENSUM=SUM + 1;END IF;END IF;END PROCESS;END behave;二位异步计数器仿真波形：检查被控制的状态机源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY CONTROL IS PORT(CLK,RST,START:IN STD_LOGIC; COUNT:IN STD_LOGIC_VECTOR(1 DOWNTO 0); IN_SEL,SHIF:OUT STD_LOGIC_VECTOR(0 to 1); STATE_OUT:OUT STD_LOGIC_VECTOR(0 to 2); DONE,CLKEN,REGCLR:OUT STD_LOGIC);END ENTITY CONTROL;ARCHITECTURE BEHAV OF CONTROL IS TYPE STATES IS(IDLE,LSB,MID,ERR,MSB); SIGNAL CURRENT_STATE,NEXT_STATE:STATES;BEGIN REG:PROCESS(RST,CLK) IS BEGIN IF RST=1THEN CURRENT_STATE=IDLE; ELSIF(CLK=1 AND CLKEVENT)THEN CURRENT_STATESTATE_OUT=000; IF START=0 THEN DONE=0; CLKEN=1; REGCLR=1; NEXT_STATE=IDLE; ELSIF START=1 THEN DONE=0; CLKEN=1; REGCLR=0; NEXT_STATESTATE_OUT=001; IF (START=0AND COUNT=00) THEN IN_SEL=00; SHIF=00; DONE=0; CLKEN=0; REGCLR=1; NEXT_STATE=MID; ELSE DONE=0; CLKEN=1; REGCLR=1; NEXT_STATESTATE_OUT=010; IF (START=0 AND COUNT=01 ) THEN IN_SEL=01; SHIF=01; DONE=0; CLKEN=0; REGCLR=1; NEXT_STATE=MID; ELSIF (START=0 AND COUNT=10) THEN IN_SEL=10; SHIF=01; DONE=0; CLKEN=0; REGCLR=1; NEXT_STATE=MSB; ELSE DONE=0; CLKEN=1; REGCLR=1; NEXT_STATESTATE_OUT=011; IF (START=0AND COUNT=11) THEN IN_SEL=11; SHIF=10; DONE=1; CLKEN=0; REGCLR=1; NEXT_STATE=IDLE; ELSE DONE=0; CLKEN=1; REGCLR=1; NEXT_STATESTATE_OUT=100; IF START=1 THEN DONE=0; CLKEN=1; REGC