MIPI协议详细介绍1ppt课件

.,MIPIProtocolIntroduction,MIPIDevelopmentTeam2010-9-2,WhatisMIPI?,MIPIstandsforMobileIndustryProcessorInterfaceMIPIAllianceisacollaborationofmobileindustryleaders.Objectivetopromoteopenstandardsforinterfacestomobileapplicationprocessors.IntendstospeeddeploymentofnewservicestomobileusersbyestablishingSpec.BoardMembersinMIPIAllianceIntel,Motorola,Nokia,NXP,Samsung,ST,TI,WhatisMIPI?,MIPIAllianceSpecificationfordisplayDCS(DisplayCommandSet)DCSisastandardizedcommandsetintendedforcommandmodedisplaymodules.DBI,DPI(DisplayBusInterface,DisplayPixelInterface)DBI：Parallelinterfacestodisplaymoduleshavingdisplaycontrollersandframebuffers.DPI：Parallelinterfacestodisplaymoduleswithouton-paneldisplaycontrollerorframebuffer.DSI,CSI(DisplaySerialInterface,CameraSerialInterface)DSIspecifiesahigh-speedserialinterfacebetweenahostprocessoranddisplaymodule.CSIspecifiesahigh-speedserialinterfacebetweenahostprocessorandcameramodule.D-PHYD-PHYprovidesthephysicallayerdefinitionforDSIandCSI.,DSILayers,DCSspec,DSIspec,D-PHYspec,Outline,D-PHYIntroductionLaneModule,StateandLinelevelsOperatingModesEscapeModeSystemPowerStatesElectricalCharacteristicsSummary,IntroductionforD-PHY,D-PHYdescribesasourcesynchronous,highspeed,lowpower,lowcostPHYAPHYconfigurationcontainsAClockLaneOneormoreDataLanesThreemainlanetypesUnidirectionalClockLaneUnidirectionalDataLaneBi-directionalDataLaneTransmissionModeLow-Powersignalingmodeforcontrolpurpose：10MHz(max)High-Speedsignalingmodeforfast-datatraffic：80Mbps1GbpsperLaneD-PHYlow-levelprotocolspecifiesaminimumdataunitofonebyteAtransmittershallsenddataLSBfirst,MSBlast.D-PHYsuitedformobileapplicationsDSI：DisplaySerialInterfaceAclocklane,Onetofourdatalanes.CSI：CameraSerialInterface,TwoDataLanePHYConfiguration,LaneModule,PHYconsistsofD-PHY(LaneModule)D-PHYmaycontainLow-PowerTransmitter(LP-TX)Low-PowerReceiver(LP-RX)High-SpeedTransmitter(HS-TX)High-SpeedReceiver(HS-RX)Low-PowerContentionDetector(LP-CD)ThreemainlanetypesUnidirectionalClockLaneMaster：HS-TX,LP-TXSlave：HS-RX,LP-RXUnidirectionalDataLaneMaster：HS-TX,LP-TXSlave：HS-RX,LP-RXBi-directionalDataLaneMaster,Slave：HS-TX,HS-RX,LP-TX,LP-RX,LP-CD,UniversalLaneModuleArchitecture,LaneStatesandLineLevels,ThetwoLP-TXsdrivethetwoLinesofaLaneindependentlyandsingle-ended.FourpossibleLow-PowerLanestates(LP-00,LP-01,LP-10,LP-11)AHS-TXdrivestheLanedifferentially.TwopossibleHighSpeedLanestates(HS-0,HS-1)DuringHStransmissiontheLPReceiversobserveLP-00ontheLinesLineLevels(typical)LP：01.2VHS：100300mV(Swing：200mV)LaneStatesLP-00,LP-01,LP-10,LP-11HS-0,HS-1,OperatingModes,TherearethreeoperatingmodesinDataLaneEscapemode,High-Speed(Burst)modeandControlmodePossibleeventsstartingfromtheStopStateofcontrolmodeEscapemoderequest(LP-11LP-10LP-00LP-01LP-00)High-Speedmoderequest(LP-11LP-01LP-00)Turnaroundrequest(LP-11LP-10LP-00LP-10LP-00),EscapeMode,EscapemodeisaspecialoperationforDataLanesusingLPstates.Withthismodesomeadditionalfunctionalitybecomesavailable：LPDT,ULPS,TriggerADataLaneshallenterEscapemodeviaLP-11LP-10LP-00LP-01LP-00OnceEscapemodeisentered,thetransmittershallsendan8-bitentrycommandtoindicatetherequestedaction.EscapemodeusesSpaced-One-HotEncoding.meanseachMarkStateisinterleavedwithaSpaceState(LP-00).SendMark-0/1followedbyaSpacetotransmitazero-bit/one-bitADataLaneshallexitEscapemodeviaLP-10LP-11Ultra-LowPowerStateDuringthisstate,theLinesareintheSpacestate(LP-00)ExitedbymeansofaMark-1statewithalengthTWAKEUP(1ms)followedbyaStopstate.,EscapeMode,ClockLaneUltra-LowPowerState,AClockLaneshallenterULPSviaLP-11LP-10LP-00exitedbymeansofaMark-1withalengthTWAKEUPfollowedbyaStopStateLP-10TWAKEUPLP-11TheminimumvalueofTWAKEUPis1ms,High-SpeedDataTransmission,Theactionofsendinghigh-speedserialdataiscalledHStransmissionorburst.Start-of-TransmissionLP-11LP-01LP-00SoT(0001_1101)HSDataTransmissionBurstAllLaneswillstartsynchronouslyButmayendatdifferenttimesTheclockLaneshallbeinHigh-Speedmode,providingaDDRClocktotheSlavesideEnd-of-TransmissionHTogglesdifferentialstateimmediatelyafterlastpayloaddatabitandkeepsthatstateforatimeTHS-TRAIL,High-SpeedClockTransmission,SwitchingtheClockLanebetweenClockTransmissionandLPModeAClockLaneisaunidirectionalLanefromMastertoSlaveInHSmode,theclockLaneprovidesalow-swing,differentialDDRclocksignal.theClockBurstalwaysstartsandendswithanHS-0state.theClockBurstalwayscontainsanevennumberoftransitions,SummaryforD-PHY,LaneModule,LaneStateandLineLevelsLaneModule：LP-TX,LP-RX,HS-TX,HS-RX,LP-CDLaneStates：LP-00,LP-01,LP-10,LP-11,HS-0,HS-1LineLevels(typical)：LP：01.2V,HS：100300mV(Swing：200mV)OperatingModesEscapeModeentryprocedure：LP-11LP-10LP-00LP-01LP-00EntryCodeLPD(10MHz)EscapeModeexitprocedure：LP-10LP-11HighSpeedModeentryprocedure：LP-11LP-01LP-00SoT(00011101)HSD(80Mbps1Gbps)HighSpeedModeexitprocedure：EoTLP-11ControlMode-BTAtransmissionprocedure：LP-11LP-10LP-00LP-10LP-00ControlMode-BTAreceiveprocedure：LP-00LP-10LP-11SystemPowerStatesLow-Powermode,High-Speedmode,Ultra-LowPowermodeFaultDetectionContentionDetection(LP-CD),WatchdogTimer,SequenceErrorDetection(ErrorReport)GlobalOperationTimingParameterClockLaneTiming,DataLaneTimingOtherTimingInitialization,BTA,Wake-UpfromULPSElectricalCharacteristicsHS-RX,LP-RX,LP-TX,LP-CD,Pincharacteristic,Clocksignal,Data-ClocktimingDCandACcharacteristic,Outline,DSIIntroductionLaneDistributor/MergerConceptualPacketStructureDataTransmissionWayProcessor-SourcedPacketsPeripheral-SourcedPacketsReverse-DirectionLPTransmissionVideoModeSummary,IntroductionforDSI,DSIisaLane-scalableinterfaceforincreasedperformance.OneClockLane/OnetoFourDataLanesDSI-compliantperipheralssupporteitheroftwobasicmodesofoperationCommandMode(SimilartoMPUIF)DataLane0：bidirectionalForreturningdata,ACKorerrorreporttohostAdditionalDataLanes：unidirectional.VideoMode(SimilartoRGBIF)DataLane0：bidirectionalorunidirectional;AdditionalDataLanes：unidirectional.VideodatashouldonlybetransmittedusingHSmode.TransmissionModeHigh-SpeedsignalingmodeLow-PowersignalingmodeForward/ReversedirectionLPtransmissionsshalluseDataLane0onlyForreturningdata,DSI-compliantsystemsshallonlyuseDataLane0inLPModePacketTypesShortPacket：4bytes(fixedlength)LongPacket：665541bytes(variablelength),TwoDataLanesHSTransmissionExample,DataTransmissionWay,SeparateTransmissions,SeparateTransmissions,KEY:LPSLowPowerStateSPShortPacketSoTStartofTransmissionLgPLongPacketEoTEndofTransmission,ShortPacketStructure,PacketHeader(4bytes)DataIdentifier(DI)*1byte：ContainstheVirtualChannel7:6andDataType5:0.PacketData*2byte：LengthisfixedattwobytesErrorCorrectionCode(ECC)*1byte：allowssingle-biterrorstobecorrectedand2-biterrorstobedetected.PacketSizeFixedlength4bytesThefirstbyteofanypacketistheDI(DataIdentifier)byte.DI7:6：Thesetwobitsidentifythedataasdirectedtooneoffourvirtualchannels.DI5:0：ThesesixbitsspecifytheDataType.,LongPacketStructure,PacketHeader(4bytes)DataIdentifier(DI)*1byte：ContainstheVirtualChannel7:6andDataType5:0.WordCount(WC)*2byte：definesthenumberofbytesintheDataPayload.ErrorCorrectionCode(ECC)*1byte：allowssingle-biterrorstobecorrectedand2-biterrorstobedetected.DataPayload(065535bytes)Length=WCbytesPacketFooter(2bytes)：ChecksumIfthepayloadhaslength0,thentheChecksumcalculationresultsinFFFFhIftheChecksumisntcalculated,theChecksumvalueis0000hPacketSize4+(065535)+2=665541bytes,DataTypesforProcessor-sourcedPackets,ErrorCorrectionCode,P7=0P6=0P5=D10D11D12D13D14D15D16D17D18D19D21D22D23P4=D4D5D6D7D8D9D16D17D18D19D20D22D23P3=D1D2D3D7D8D9D13D14D15D19D20D21D23P2=D0D2D3D5D6D9D11D12D15D18D20D21D22P1=D0D1D3D4D6D8D10D12D14D17D20D21D22D23P0=D0D1D2D4D5D7D10D11D13D16D20D21D22D23,Checksum,unsignedcharxx=0 x01,0 x5a,0 x5a,0 x03,0 x08,0 x2A,0 x00,0 x01,0 x00,0 xF8,0 x00,0 xF6,0 x57,0 x00,0X00,0 xE5;typedefunsignedshortU16;typedefunsignedcharU8;U16CRC_test;U16crc16_update(U16crc,U8a);intmain()U16crc,i;crc=0 xFFFF;for(i=0;i1)0 x8408;elsecrc=(crc1);returncrc;,Peripheral-to-ProcessorLPTransmissions,DetailedformatdescriptionPacketstructureforperipheral-to-processortransactionsisthesameasfortheprocessor-to-peripheraldirectionForasingle-bytereadresponse,validdatashallbereturnedinthefirstbyteThesecondbyteshallbesentas00hIftheperipheraldoesnotsupportChecksumitshallreturn0000h,Peripheral-to-ProcessorLPTransmissions,Peripheral-to-processortransactionsareoffourbasictypesTearingEffect(TE)：triggermessage(BAh)Acknowledge：triggermessage(84h)AcknowledgeandErrorReport：shortpacket(DataTypeis02h)ResponsetoReadRequest：shortpacketorlongpacketGenericReadResponse、DCSR