IBMPCAT硬件架构与动作原理51页.PPT

1,IBMPC/AT硬體架構與動作原理,(1).PC/ATOriginalSchematics1.TheBlocksStructure2.Decoder3.DataBusFlow4.AddressBusFlow5.OtherSignalsandISA(2).KT9System(ATIRS200MP+ALIM1535+)1.SystemBlockDiagram2.SystemStartSteps3.POST(Power-OnSelfTest)4.BIOS,(3).Differences(versusCPU/PCI/ISA)1.Introduction2.CPUBusCycle3.PCI(4).IntroductiontheCompactPCI,byJRJen01-12-05HomWo03-12-29,2,IBMPC/AT原版電路之功能方塊的內容,1.系統時脈電路2.DRAM解碼電路3.RAS&CAS產生電路4.DRAM偵測電路5.DRAM定址電路6.ROMAccess電路7.Decoder8.等待電路9.刷新要求電路,10.DMA控制電路11.系統中斷電路12.系統計時/計數器電路13.鍵盤控制器電路14.及時時脈電路15.NMI控制電路16.Shut-downLogic,3,Figure:Decoder(PC/AToriginalschematic),4,5,IBMPC/ATIOPortAddresses,1.Range00HFFH:Systemboard2.Range1003FFH:I/OChannel3.00H1FH:DMAController1Registers4.20H3FH:InterruptController1Register5.40H5FH:ProgrammableInterruptTimer6.60H64H:keyboardControllerbuffer7.70H:CMOSRAMaddressregisterport,6,8.71H:CMOSRAMdataregisterPort9.80H:ManufacturingTestPort10.81H8FH:DMApagetableaddressreg.11.A0HBFH:Programmableinterruptctrl212.C0HDFH:DMAController2Register13.F0HFFH:MathCoprocessorregs.14.170H177H:Fixeddisk1registers15.1F0H1F7H:Fixeddisk0registers16.200H20FH:Gamecontrolport17.201H:GamePortI/OData18.278H27AH:ParallelPort3registers19.2F8H2FFH:SerialPort2registers,7,20.370H377H:DisketteController1reg21.378H37AH:ParallelPort2registers22.3BCH3BEH:ParallelPort1registers23.3F0H3FFH:DisketteController0reg24.3F8H3FFH:SerialPort1registers25.3C0H3CFH:VGAI/OPortregisters,8,8042ControlRegister(I/OPortAddress:61H),Read/WritestatusBit7=1ParitycheckBit6=1ChannelcheckBit5=1Timer2outputBit4=1TogglewitheachrefreshrequestBit3=1ChannelcheckenabledBit2=1ParitycheckenabledBit1=1SpeakdataenabledBit0=1Timer2gatetospeakerenabled,9,10,11,外在緩衝器控制線路,外在緩衝器,ExternalBuffer的OIR控制得分析,12,SA0SA19,13,HLDA,65,U74,80286,ALE,5,U83,82288,RESET,12,U82,82284,11,12,13,U11,ALS08,4,5,6,U80,ALS32,Y,5,Y,7,Y,3,Y,9,A15,10,A,13,A,17,A,11,G,19,U75,ALS244,CPUHLDA,HLDA,-MASTER,ALE,+ACK,GATEALE,+RESET,HLDA,AEN,BALE,RESETDRV,AEN,BALE,RESETDRV:ATSlotsignals.,AEN,BALE,RESETDRV信號的流程,FromATslot,HLDA,14,15,16,17,KT9SystemBlockDiagram,18,KT9PowerOnBlockDiagram,19,SystemStartSteps(1),1.PowerON/OFFButtonPC87570(PCU)2.PC87570M1535+(SouthBridge)3.M1535+PC87570SUSPower(3VSUS、5VSUS)4.PC87570MainPower(3V、5V、2.5V)VHcore,20,1.WhenwepushthePowerButton,thesignal-NBSWONwillbegeneratedandsendtothePCU(PC87570).2.AsthePCUreceivesthe-NBSWON,itwillsendthe-DNBSWONtothesouthbridge(M1535+).3.ThentheSBasserts-SUSBand-SUSCsignalstothePCU.4.ThePCUwillsendtheSUSON,MAINONandVRONforsuspendpower,mainpowerandVHcoregenerating.,SystemStartSteps(1),21,4.1PC87570,SUSON,2.5VSUS,12VS,3VSUS,5VSUS,4.2PC87570,MAINON,3VAGP,2.5V,12V,VTT_DDR,3V,5V,SUSD,MAIND,4.3PC87570,-VRON,2.5VSUS,VHcore,22,SystemStartSteps(2),HWPG,5.MAX1632,HWPG-POWER,PC87570,6.PC87570,NPWROK,NB_PWROK,RS200MP(NB),NB_PWROK,PWROK,7.,SB_PWROK,M1535+,CPU_PWRGD,PWRGOOD,CPU,23,SystemStartSteps(3),-SYS_RST,8.M1535+,-PCI_RST,-PCI_RST,9.,-NB_PCIRST,RS200MP,SB_PWROK,-PCIRST,10.RS200MP,-CPU_RST,CPU,*CPUandallI/Odeviceshavebeenreset.,24,SystemStartSteps(4),11.CPUMemoryCodeReadNorthBridge-Address(A31#A3#):FFFFFFF012.NorthBridge:CPUCommandPCICommandCPUAddressPCIAddress13.NorthBridgeMemoryReadSouthBridge-Address(AD31AD0):FFFFFFF014.SouthBridge:PCICommandISACommandPCIAddressISAAddress,25,SystemStartSteps(4),11.CPUwillgeneratethefirstcommand-MemoryCodeReadtotheNorthBridge,andtheHostaddress-(A31#A3#):FFFFFFF0.12.WhentheNBreceivestheCPUcommandandHostaddress,ItwilltranslatetheCPUcommandtoPCIcommand-(MemoryRead),andtranslatetheHostAddresstothePCIaddress-(AD31#AD0#):FFFFFFF0.13.ThentheNBsendsthePCIcommandandPCIaddresstotheSouthBridgeviathePCIBus.14.AStheSBreceivesthePCIcommandandPCIaddress,itwilltranslatethePCIcommandtotheISAcommand-(MEMR#)andthePCIaddresstotheISAaddress-(A19A0):FFFFF.,26,SystemStartSteps(5),15.SouthBridgeMEMR#SystemROM-Address(SA17SA0):1FFF016.ROMDataISADataBusSouthBridge17.SouthBridgePCIDataBusNorthBridge18.NorthBridgeHostDataBusCPU19.CPU:DecodeandExecute(GoToStep11:Decode&Execute),27,SystemStartSteps(5),15.THESBwilldrivetheMEMR#commandtotheSystemROMandaccesstheROMaddress(SA17SA0):1FFF016.SotheROMDatawillbetransferredtoSouthBridgethroughtheISABus17.AndthenthroughthePCIBus,theSouthBridgewillsendthePCIdatetotheNorthBridge18.AtthelasttheNorthBridgewillsendHostdatatotheCPUthroughtheHostBus.19.AftertheCPUfetchthehostdatawhichistransferredfromNorthBridge,itbeginstoDecode&Execute(GoToStep11:Decode&Execute).,28,ThefirstExecutionInstructioninPCAT,CPUAddress:A31A3=FFFFFFF0CPU:CS:IP=F000:FFF0FFFF0ISAAddress:SA17SA0=1FFF0ISAData:1FFF0:EA5BE000F030372F1FFF8:31352F393900FC005.EA5BE000F0=LongJumpF000:E05B30372F31352F3939=07/15/99,29,POST(Power-OnSelfTest)Process,POSTtestsandinitializesthefollowing:Thecentralprocessingunit(CPU)TheROMBIOS(checksum)TheCMOSRAMTheIntel8237DMAControllerThekeyboardcontrollerThebase64KSystemRAMTheProgrammableInterruptcontroller,30,8.TheProgrammableInterruptTimer9.Thecachecontroller10.COMSRAMconfigurationdata11.TheCRTcontroller12.RAMmemoryabove64K13.Thekeyboard14.DiskettedriveAavailability15.Theserialinterfacecircuitry16.Thediskettecontroller17.Thefixeddiskcontroller18.Anyadditionalhardware,31,AWARDBIOSPOSTTestcodelisting,32,33,34,IBMPC/ATSystemRAMDataArea,(1).Range:00Hto3FFHInterruptVectorTableInterruptVectorStoredasoffset/segmentformat(2).Range:400Hto4FFHBIOSDataAreaDatadefinitionsrelatedtoBIOSfixeddisk,diskette,Keyboard,video,35,ThefirsttwowordsofexpansionROMarea,VGABIOS(CS:IP=C000:0000)ROMByteValue055H1AAH2ROMLengthin512-byteblocks3EntrypointforROMinitialization(viaFARCALL),36,Differences(vs.CPU/PCI/ISA),CPUPCIISA1.Speed66/100/13333/668MHz2.PowerVcore&Vio3.3V5V3.AddressBus32/(36)32/6424bit4.DataBus6432/6416bit5.Address/DataSeparateSharedSeparate,37,6.ControlBus(Commands/Controlsignals)CPUPCIISA6.1Types8/(32)1646.2StartADS-FRAME-BALE6.3EndReady-IRDY-&TRDY-IOCHRDY7.IDVPID0:3IDSEL-(Decoder),38,39,BUSCYCLEDEFINITION,40,TransactionTypeDefinedbyREQ#Signals,41,TableLEN1:0#SignalDataTransferLengths,TableASZ1:0#SignalDecode,42,POWERGOODRelationshipatPower-On,VCCcore,VCCL2,PWRGOOD,RESET#,Clock,1ms,Ratio,BCLK,43,SystemBusToCoreFrequencyMultiplierConfiguration,44,45,ADDRESSPHASE,DATAPHASE,DATAPHASE,DATAPHASE,BUSTRANSACTION,Figure:BasicReadOperation,1,2,3,4,5,6,7,8,9,CLK,FRAME#,AD,ADDRESS,DATA-1,DATA-2,DATA-3,C/BE#,BUSCMD,BE#S,IRDY#,WAIT,DATATRANSFER,WAIT,DATATRANSFER,WAIT,DATATRANSFER,TRDY#,DEVSEL#,46,CommandDefinition,C/BE3:0#CommandType0000InterruptAcknowledge0001SpecialCycle0010I/ORead0011I/OWrite0100Reserved0101Reserved0110MemoryRead0111MemoryWrite1000Reserved1001Reserved1010ConfigurationRead1011ConfigurationWrite1100MemoryReadMultiple1101DualAddressCycle1110MemoryReadLine1111MemoryWriteandInvalidate,47,DATAPHASE,DATAPHASE,DATAPHASE,BUSTRANSACTION,1,2,3,4,5,6,7,8,9,CLK,FRAME#,AD,ADDRESS,DATA-1,DATA-3,C/BE#,BUSCMD,BE#S-3,IRDY#,WAIT,DATATRANSFER,WAIT,DATATRANSFER,WAIT,DATATRANSFER,TRDY#,DEVSEL#,DATA-2,BE#S-1,BE#S-2,ADDRESSPHASE,Figure:BasicWriteOperation,48,PCICOMPLIANTDEVICE,AD63:32,C/BE7:4#,AD31:00,C/BE