基于FPGA的SDRAM实验说明书

1/MEGAFUNCTIONWIZARDALTPLL/GENERATIONSTANDARD/VERSIONWM10/MODULEALTPLL/FILENAMECLK_CTRLV/MEGAFUNCTIONNAMES/ALTPLL/SIMULATIONLIBRARYFILESS/ALTERA_MF/THISISAWIZARDGENERATEDFILEDONOTEDITTHISFILE/110BUILD20807/03/2011SP1SJFULLVERSION/COPYRIGHTC19912011ALTERACORPORATION/YOURUSEOFALTERACORPORATIONSDESIGNTOOLS,LOGICFUNCTIONS/ANDOTHERSOFTWAREANDTOOLS,ANDITSAMPPPARTNERLOGIC/FUNCTIONS,ANDANYOUTPUTFILESFROMANYOFTHEFOREGOING/INCLUDINGDEVICEPROGRAMMINGORSIMULATIONFILES,ANDANY/ASSOCIATEDDOCUMENTATIONORINFORMATIONAREEXPRESSLYSUBJECT/TOTHETERMSANDCONDITIONSOFTHEALTERAPROGRAMLICENSE/SUBSCRIPTIONAGREEMENT,ALTERAMEGACOREFUNCTIONLICENSE/AGREEMENT,OROTHERAPPLICABLELICENSEAGREEMENT,INCLUDING,/WITHOUTLIMITATION,THATYOURUSEISFORTHESOLEPURPOSEOF/PROGRAMMINGLOGICDEVICESMANUFACTUREDBYALTERAANDSOLDBY/ALTERAORITSAUTHORIZEDDISTRIBUTORSPLEASEREFERTOTHE/APPLICABLEAGREEMENTFORFURTHERDETAILS/SYNOPSYSTRANSLATE_OFFTIMESCALE1PS/1PS/SYNOPSYSTRANSLATE_ONMODULECLK_CTRLARESET,INCLK0,C0,C1,C2,2LOCKEDINPUTARESETINPUTINCLK0OUTPUTC0OUTPUTC1OUTPUTC2OUTPUTLOCKEDIFNDEFALTERA_RESERVED_QIS/SYNOPSYSTRANSLATE_OFFENDIFTRI0ARESETIFNDEFALTERA_RESERVED_QIS/SYNOPSYSTRANSLATE_ONENDIFWIRE50SUB_WIRE0WIRESUB_WIRE2WIRE00SUB_WIRE71H0WIRE22SUB_WIRE4SUB_WIRE022WIRE00SUB_WIRE3SUB_WIRE000WIRE11SUB_WIRE1SUB_WIRE011WIREC1SUB_WIRE1WIRELOCKEDSUB_WIRE2WIREC0SUB_WIRE3WIREC2SUB_WIRE4WIRESUB_WIRE5INCLK0WIRE10SUB_WIRE6SUB_WIRE7,SUB_WIRE5ALTPLLALTPLL_COMPONENTARESETARESET,INCLKSUB_WIRE6,CLKSUB_WIRE0,LOCKEDSUB_WIRE2,ACTIVECLOCK,CLKBAD,CLKENA61B1,CLKLOSS,CLKSWITCH1B0,CONFIGUPDATE1B0,ENABLE0,ENABLE1,EXTCLK,EXTCLKENA41B1,3FBIN1B1,FBMIMICBIDIR,FBOUT,FREF,ICDRCLK,PFDENA1B1,PHASECOUNTERSELECT41B1,PHASEDONE,PHASESTEP1B1,PHASEUPDOWN1B1,PLLENA1B1,SCANACLR1B0,SCANCLK1B0,SCANCLKENA1B1,SCANDATA1B0,SCANDATAOUT,SCANDONE,SCANREAD1B0,SCANWRITE1B0,SCLKOUT0,SCLKOUT1,VCOOVERRANGE,VCOUNDERRANGEDEFPARAMALTPLL_COMPONENTCLK0_DIVIDE_BY1,ALTPLL_COMPONENTCLK0_DUTY_CYCLE50,ALTPLL_COMPONENTCLK0_MULTIPLY_BY5,ALTPLL_COMPONENTCLK0_PHASE_SHIFT“0“,ALTPLL_COMPONENTCLK1_DIVIDE_BY1,ALTPLL_COMPONENTCLK1_DUTY_CYCLE50,ALTPLL_COMPONENTCLK1_MULTIPLY_BY1,ALTPLL_COMPONENTCLK1_PHASE_SHIFT“0“,ALTPLL_COMPONENTCLK2_DIVIDE_BY1,ALTPLL_COMPONENTCLK2_DUTY_CYCLE50,ALTPLL_COMPONENTCLK2_MULTIPLY_BY5,ALTPLL_COMPONENTCLK2_PHASE_SHIFT“5000“,ALTPLL_COMPONENTCOMPENSATE_CLOCK“CLK0“,ALTPLL_COMPONENTGATE_LOCK_SIGNAL“NO“,ALTPLL_COMPONENTINCLK0_INPUT_FREQUENCY50000,ALTPLL_COMPONENTINTENDED_DEVICE_FAMILY“CYCLONEII“,ALTPLL_COMPONENTINVALID_LOCK_MULTIPLIER5,ALTPLL_COMPONENTLPM_HINT“CBX_MODULE_PREFIXCLK_CTRL“,ALTPLL_COMPONENTLPM_TYPE“ALTPLL“,ALTPLL_COMPONENTOPERATION_MODE“NORMAL“,4ALTPLL_COMPONENTPORT_ACTIVECLOCK“PORT_UNUSED“,ALTPLL_COMPONENTPORT_ARESET“PORT_USED“,ALTPLL_COMPONENTPORT_CLKBAD0“PORT_UNUSED“,ALTPLL_COMPONENTPORT_CLKBAD1“PORT_UNUSED“,ALTPLL_COMPONENTPORT_CLKLOSS“PORT_UNUSED“,ALTPLL_COMPONENTPORT_CLKSWITCH“PORT_UNUSED“,ALTPLL_COMPONENTPORT_CONFIGUPDATE“PORT_UNUSED“,ALTPLL_COMPONENTPORT_FBIN“PORT_UNUSED“,ALTPLL_COMPONENTPORT_INCLK0“PORT_USED“,ALTPLL_COMPONENTPORT_INCLK1“PORT_UNUSED“,ALTPLL_COMPONENTPORT_LOCKED“PORT_USED“,ALTPLL_COMPONENTPORT_PFDENA“PORT_UNUSED“,ALTPLL_COMPONENTPORT_PHASECOUNTERSELECT“PORT_UNUSED“,ALTPLL_COMPONENTPORT_PHASEDONE“PORT_UNUSED“,ALTPLL_COMPONENTPORT_PHASESTEP“PORT_UNUSED“,ALTPLL_COMPONENTPORT_PHASEUPDOWN“PORT_UNUSED“,ALTPLL_COMPONENTPORT_PLLENA“PORT_UNUSED“,ALTPLL_COMPONENTPORT_SCANACLR“PORT_UNUSED“,ALTPLL_COMPONENTPORT_SCANCLK“PORT_UNUSED“,ALTPLL_COMPONENTPORT_SCANCLKENA“PORT_UNUSED“,ALTPLL_COMPONENTPORT_SCANDATA“PORT_UNUSED“,ALTPLL_COMPONENTPORT_SCANDATAOUT“PORT_UNUSED“,ALTPLL_COMPONENTPORT_SCANDONE“PORT_UNUSED“,ALTPLL_COMPONENTPORT_SCANREAD“PORT_UNUSED“,ALTPLL_COMPONENTPORT_SCANWRITE“PORT_UNUSED“,ALTPLL_COMPONENTPORT_CLK0“PORT_USED“,ALTPLL_COMPONENTPORT_CLK1“PORT_USED“,ALTPLL_COMPONENTPORT_CLK2“PORT_USED“,ALTPLL_COMPONENTPORT_CLK3“PORT_UNUSED“,ALTPLL_COMPONENTPORT_CLK4“PORT_UNUSED“,ALTPLL_COMPONENTPORT_CLK5“PORT_UNUSED“,ALTPLL_COMPONENTPORT_CLKENA0“PORT_UNUSED“,ALTPLL_COMPONENTPORT_CLKENA1“PORT_UNUSED“,ALTPLL_COMPONENTPORT_CLKENA2“PORT_UNUSED“,ALTPLL_COMPONENTPORT_CLKENA3“PORT_UNUSED“,ALTPLL_COMPONENTPORT_CLKENA4“PORT_UNUSED“,ALTPLL_COMPONENTPORT_CLKENA5“PORT_UNUSED“,ALTPLL_COMPONENTPORT_EXTCLK0“PORT_UNUSED“,ALTPLL_COMPONENTPORT_EXTCLK1“PORT_UNUSED“,ALTPLL_COMPONENTPORT_EXTCLK2“PORT_UNUSED“,ALTPLL_COMPONENTPORT_EXTCLK3“PORT_UNUSED“,ALTPLL_COMPONENTVALID_LOCK_MULTIPLIER15ENDMODULE/CNXFILERETRIEVALINFO/RETRIEVALINFOPRIVATEACTIVECLK_CHECKSTRING“0“/RETRIEVALINFOPRIVATEBANDWIDTHSTRING“1000“/RETRIEVALINFOPRIVATEBANDWIDTH_FEATURE_ENABLEDSTRING“0“/RETRIEVALINFOPRIVATEBANDWIDTH_FREQ_UNITSTRING“MHZ“/RETRIEVALINFOPRIVATEBANDWIDTH_PRESETSTRING“LOW“/RETRIEVALINFOPRIVATEBANDWIDTH_USE_AUTOSTRING“1“/RETRIEVALINFOPRIVATEBANDWIDTH_USE_CUSTOMSTRING“0“/RETRIEVALINFOPRIVATEBANDWIDTH_USE_PRESETSTRING“0“/RETRIEVALINFOPRIVATECLKBAD_SWITCHOVER_CHECKSTRING“0“/RETRIEVALINFOPRIVATECLKLOSS_CHECKSTRING“0“/RETRIEVALINFOPRIVATECLKSWITCH_CHECKSTRING“1“/RETRIEVALINFOPRIVATECNX_NO_COMPENSATE_RADIOSTRING“0“/RETRIEVALINFOPRIVATECREATE_CLKBAD_CHECKSTRING“0“/RETRIEVALINFOPRIVATECREATE_INCLK1_CHECKSTRING“0“/RETRIEVALINFOPRIVATECUR_DEDICATED_CLKSTRING“C0“/RETRIEVALINFOPRIVATECUR_FBIN_CLKSTRING“C0“/RETRIEVALINFOPRIVATEDEVICE_SPEED_GRADESTRING“8“/RETRIEVALINFOPRIVATEDIV_FACTOR0NUMERIC“1“/RETRIEVALINFOPRIVATEDIV_FACTOR1NUMERIC“1“/RETRIEVALINFOPRIVATEDIV_FACTOR2NUMERIC“1“/RETRIEVALINFOPRIVATEDUTY_CYCLE0STRING“5000000000“/RETRIEVALINFOPRIVATEDUTY_CYCLE1STRING“5000000000“/RETRIEVALINFOPRIVATEDUTY_CYCLE2STRING“5000000000“/RETRIEVALINFOPRIVATEEFF_OUTPUT_FREQ_VALUE0STRING“100000000“/RETRIEVALINFOPRIVATEEFF_OUTPUT_FREQ_VALUE1STRING“20000000“/RETRIEVALINFOPRIVATEEFF_OUTPUT_FREQ_VALUE2STRING“100000000“/RETRIEVALINFOPRIVATEEXPLICIT_SWITCHOVER_COUNTERSTRING“0“/RETRIEVALINFOPRIVATEEXT_FEEDBACK_RADIOSTRING“0“/RETRIEVALINFOPRIVATEGLOCKED_COUNTER_EDIT_CHANGEDSTRING“1“/RETRIEVALINFOPRIVATEGLOCKED_FEATURE_ENABLEDSTRING“1“/RETRIEVALINFOPRIVATEGLOCKED_MODE_CHECKSTRING“0“/RETRIEVALINFOPRIVATEGLOCK_COUNTER_EDITNUMERIC“1048575“/RETRIEVALINFOPRIVATEHAS_MANUAL_SWITCHOVERSTRING“1“/RETRIEVALINFOPRIVATEINCLK0_FREQ_EDITSTRING“20000“/RETRIEVALINFOPRIVATEINCLK0_FREQ_UNIT_COMBOSTRING“MHZ“/RETRIEVALINFOPRIVATEINCLK1_FREQ_EDITSTRING“100000“/RETRIEVALINFOPRIVATEINCLK1_FREQ_EDIT_CHANGEDSTRING“1“/RETRIEVALINFOPRIVATEINCLK1_FREQ_UNIT_CHANGEDSTRING“1“/RETRIEVALINFOPRIVATEINCLK1_FREQ_UNIT_COMBOSTRING“MHZ“6/RETRIEVALINFOPRIVATEINTENDED_DEVICE_FAMILYSTRING“CYCLONEII“/RETRIEVALINFOPRIVATEINT_FEEDBACK_MODE_RADIOSTRING“1“/RETRIEVALINFOPRIVATELOCKED_OUTPUT_CHECKSTRING“1“/RETRIEVALINFOPRIVATELONG_SCAN_RADIOSTRING“1“/RETRIEVALINFOPRIVATELVDS_MODE_DATA_RATESTRING“NOTAVAILABLE“/RETRIEVALINFOPRIVATELVDS_MODE_DATA_RATE_DIRTYNUMERIC“0“/RETRIEVALINFOPRIVATELVDS_PHASE_SHIFT_UNIT0STRING“DEG“/RETRIEVALINFOPRIVATELVDS_PHASE_SHIFT_UNIT1STRING“DEG“/RETRIEVALINFOPRIVATELVDS_PHASE_SHIFT_UNIT2STRING“DEG“/RETRIEVALINFOPRIVATEMIG_DEVICE_SPEED_GRADESTRING“ANY“/RETRIEVALINFOPRIVATEMIRROR_CLK0STRING“0“/RETRIEVALINFOPRIVATEMIRROR_CLK1STRING“0“/RETRIEVALINFOPRIVATEMIRROR_CLK2STRING“0“/RETRIEVALINFOPRIVATEMULT_FACTOR0NUMERIC“5“/RETRIEVALINFOPRIVATEMULT_FACTOR1NUMERIC“1“/RETRIEVALINFOPRIVATEMULT_FACTOR2NUMERIC“5“/RETRIEVALINFOPRIVATENORMAL_MODE_RADIOSTRING“1“/RETRIEVALINFOPRIVATEOUTPUT_FREQ0STRING“10000000000“/RETRIEVALINFOPRIVATEOUTPUT_FREQ1STRING“10000000000“/RETRIEVALINFOPRIVATEOUTPUT_FREQ2STRING“10000000000“/RETRIEVALINFOPRIVATEOUTPUT_FREQ_MODE0STRING“0“/RETRIEVALINFOPRIVATEOUTPUT_FREQ_MODE1STRING“0“/RETRIEVALINFOPRIVATEOUTPUT_FREQ_MODE2STRING“0“/RETRIEVALINFOPRIVATEOUTPUT_FREQ_UNIT0STRING“MHZ“/RETRIEVALINFOPRIVATEOUTPUT_FREQ_UNIT1STRING“MHZ“/RETRIEVALINFOPRIVATEOUTPUT_FREQ_UNIT2STRING“MHZ“/RETRIEVALINFOPRIVATEPHASE_RECONFIG_FEATURE_ENABLEDSTRING“0“/RETRIEVALINFOPRIVATEPHASE_RECONFIG_INPUTS_CHECKSTRING“0“/RETRIEVALINFOPRIVATEPHASE_SHIFT0STRING“000000000“/RETRIEVALINFOPRIVATEPHASE_SHIFT1STRING“000000000“/RETRIEVALINFOPRIVATEPHASE_SHIFT2STRING“500000000“/RETRIEVALINFOPRIVATEPHASE_SHIFT_STEP_ENABLED_CHECKSTRING“0“/RETRIEVALINFOPRIVATEPHASE_SHIFT_UNIT0STRING“DEG“/RETRIEVALINFOPRIVATEPHASE_SHIFT_UNIT1STRING“DEG“/RETRIEVALINFOPRIVATEPHASE_SHIFT_UNIT2STRING“NS“/RETRIEVALINFOPRIVATEPLL_ADVANCED_PARAM_CHECKSTRING“0“/RETRIEVALINFOPRIVATEPLL_ARESET_CHECKSTRING“1“/RETRIEVALINFOPRIVATEPLL_AUTOPLL_CHECKNUMERIC“1“/RETRIEVALINFOPRIVATEPLL_ENA_CHECKSTRING“0“/RETRIEVALINFOPRIVATEPLL_ENHPLL_CHECKNUMERIC“0“/RETRIEVALINFOPRIVATEPLL_FASTPLL_CHECKNUMERIC“0“/RETRIEVALINFOPRIVATEPLL_FBMIMIC_CHECKSTRING“0“/RETRIEVALINFOPRIVATEPLL_LVDS_PLL_CHECKNUMERIC“0“/RETRIEVALINFOPRIVATEPLL_PFDENA_CHECKSTRING“0“7/RETRIEVALINFOPRIVATEPLL_TARGET_HARCOPY_CHECKNUMERIC“0“/RETRIEVALINFOPRIVATEPRIMARY_CLK_COMBOSTRING“INCLK0“/RETRIEVALINFOPRIVATERECONFIG_FILESTRING“CLK_CTRLMIF“/RETRIEVALINFOPRIVATESACN_INPUTS_CHECKSTRING“0“/RETRIEVALINFOPRIVATESCAN_FEATURE_ENABLEDSTRING“0“/RETRIEVALINFOPRIVATESELF_RESET_LOCK_LOSSSTRING“0“/RETRIEVALINFOPRIVATESHORT_SCAN_RADIOSTRING“0“/RETRIEVALINFOPRIVATESPREAD_FEATURE_ENABLEDSTRING“0“/RETRIEVALINFOPRIVATESPREAD_FREQSTRING“50000“/RETRIEVALINFOPRIVATESPREAD_FREQ_UNITSTRING“KHZ“/RETRIEVALINFOPRIVATESPREAD_PERCENTSTRING“0500“/RETRIEVALINFOPRIVATESPREAD_USESTRING“0“/RETRIEVALINFOPRIVATESRC_SYNCH_COMP_RADIOSTRING“0“/RETRIEVALINFOPRIVATESTICKY_CLK0STRING“1“/RETRIEVALINFOPRIVATESTICKY_CLK1STRING“1“/RETRIEVALINFOPRIVATESTICKY_CLK2STRING“1“/RETRIEVALINFOPRIVATESWITCHOVER_COUNT_EDITNUMERIC“1“/RETRIEVALINFOPRIVATESWITCHOVER_FEATURE_ENABLEDSTRING“1“/RETRIEVALINFOPRIVATESYNTH_WRAPPER_GEN_POSTFIXSTRING“0“/RETRIEVALINFOPRIVATEUSE_CLK0STRING“1“/RETRIEVALINFOPRIVATEUSE_CLK1STRING“1“/RETRIEVALINFOPRIVATEUSE_CLK2STRING“1“/RETRIEVALINFOPRIVATEUSE_CLKENA0STRING“0“/RETRIEVALINFOPRIVATEUSE_CLKENA1STRING“0“/RETRIEVALINFOPRIVATEUSE_CLKENA2STRING“0“/RETRIEVALINFOPRIVATEUSE_MIL_SPEED_GRADENUMERIC“0“/RETRIEVALINFOPRIVATEZERO_DELAY_RADIOSTRING“0“/RETRIEVALINFOLIBRARYALTERA_MFALTERA_MFALTERA_MF_COMPONENTSALL/RETRIEVALINFOCONSTANTCLK0_DIVIDE_BYNUMERIC“1“/RETRIEVALINFOCONSTANTCLK0_DUTY_CYCLENUMERIC“50“/RETRIEVALINFOCONSTANTCLK0_MULTIPLY_BYNUMERIC“5“/RETRIEVALINFOCONSTANTCLK0_PHASE_SHIFTSTRING“0“/RETRIEVALINFOCONSTANTCLK1_DIVIDE_BYNUMERIC“1“/RETRIEVALINFOCONSTANTCLK1_DUTY_CYCLENUMERIC“50“/RETRIEVALINFOCONSTANTCLK1_MULTIPLY_BYNUMERIC“1“/RETRIEVALINFOCONSTANTCLK1_PHASE_SHIFTSTRING“0“/RETRIEVALINFOCONSTANTCLK2_DIVIDE_BYNUMERIC“1“/RETRIEVALINFOCONSTANTCLK2_DUTY_CYCLENUMERIC“50“/RETRIEVALINFOCONSTANTCLK2_MULTIPLY_BYNUMERIC“5“/RETRIEVALINFOCONSTANTCLK2_PHASE_SHIFTSTRING“5000“/RETRIEVALINFOCONSTANTCOMPENSATE_CLOCKSTRING“CLK0“/RETRIEVALINFOCONSTANTGATE_LOCK_SIGNALSTRING“NO“/RETRIEVALINFOCONSTANTINCLK0_INPUT_FREQUENCYNUMERIC“50000“/RETRIEVALINFOCONSTANTINTENDED_DEVICE_FAMILYSTRING“CYCLONEII“8/RETRIEVALINFOCONSTANTINVALID_LOCK_MULTIPLIERNUMERIC“5“/RETRIEVALINFOCONSTANTLPM_TYPESTRING“ALTPLL“/RETRIEVALINFOCONSTANTOPERATION_MODESTRING“NORMAL“/RETRIEVALINFOCONSTANTPORT_ACTIVECLOCKSTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_ARESETSTRING“PORT_USED“/RETRIEVALINFOCONSTANTPORT_CLKBAD0STRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_CLKBAD1STRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_CLKLOSSSTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_CLKSWITCHSTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_CONFIGUPDATESTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_FBINSTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_INCLK0STRING“PORT_USED“/RETRIEVALINFOCONSTANTPORT_INCLK1STRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_LOCKEDSTRING“PORT_USED“/RETRIEVALINFOCONSTANTPORT_PFDENASTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_PHASECOUNTERSELECTSTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_PHASEDONESTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_PHASESTEPSTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_PHASEUPDOWNSTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_PLLENASTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_SCANACLRSTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_SCANCLKSTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_SCANCLKENASTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_SCANDATASTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_SCANDATAOUTSTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_SCANDONESTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_SCANREADSTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_SCANWRITESTRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_CLK0STRING“PORT_USED“/RETRIEVALINFOCONSTANTPORT_CLK1STRING“PORT_USED“/RETRIEVALINFOCONSTANTPORT_CLK2STRING“PORT_USED“/RETRIEVALINFOCONSTANTPORT_CLK3STRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_CLK4STRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_CLK5STRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_CLKENA0STRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_CLKENA1STRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_CLKENA2STRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_CLKENA3STRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_CLKENA4STRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_CLKENA5STRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_EXTCLK0STRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_EXTCLK1STRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_EXTCLK2STRING“PORT_UNUSED“/RETRIEVALINFOCONSTANTPORT_EXTCLK3STRING“PORT_UNUSED“9/RETRIEVALINFOCONSTANTVALID_LOCK_MULTIPLIERNUMERIC“1“/RETRIEVALINFOUSED_PORTCLK0060OUTPUT_CLK_EXTVCC“CLK50“/RETRIEVALINFOUSED_PORTEXTCLK0040OUTPUT_CLK_EXTVCC“EXTCLK30“/RETRIEVALINFOUSED_PORTARESET0000INPUTGND“ARESET“/RETRIEVALINFOUSED_PORTC00000OUTPUT_CLK_EXTVCC“C0“/RETRIEVALINFOUSED_PORTC10000OUTPUT_CLK_EXTVCC“C1“/RETRIEVALINFOUSED_PORTC20000OUTPUT_CLK_EXTVCC“C2“/RETRIEVALINFOUSED_PORTINCLK00000INPUT_CLK_EXTGND“INCLK0“/RETRIEVALINFOUSED_PORTLOCKED0000OUTPUTGND“LOCKED“/RETRIEVALINFOCONNECTARESET0000ARESET0000/RETRIEVALINFOCONNECTINCLK0011GND0000/RETRIEVALINFOCONNECTINCLK0010INCLK00000/RETRIEVALINFOCONNECTC00000CLK0010/RETRIEVALINFOCONNECTC10000CLK0011/RETRIEVALINFOCONNECTC20000CLK0012/RETRIEVALINFOCONNECTLOCKED0000LOCKED0000/RETRIEVALINFOGEN_FILETYPE_NORMALCLK_CTRLVTRUE/RETRIEVALINFOGEN_FILETYPE_NORMALCLK_CTRLPPFTRUE/RETRIEVALINFOGEN_FILETYPE_NORMALCLK_CTRLINCFALSE/RETRIEVALINFOGEN_FILETYPE_NORMALCLK_CTRLCMPFALSE/RETRIEVALINFOGEN_FILETYPE_NORMALCLK_CTRLBSFFALSE/RETRIEVALINFOGEN_FILETYPE_NORMALCLK_CTRL_INSTVTRUE/RETRIEVALINFOGEN_FILETYPE_NORMALCLK_CTRL_BBVTRUE/RETRIEVALINFOLIB_FILEALTERA_MF/RETRIEVALINFOCBX_MODULE_PREFIXONTIMESCALE1NS/1PS/COMPANY/SDRAM接口说明上电复位时，SDRAM会自动等待200US然后进行初始化，具体模式寄存器的设置参看SDRAM_CTRL模块。SDRAM的操作控制SYS_EN1,SYS_R_WN0,SYS_ADDR,SYS_DATA_IN进行SDRAM数据写入操作；控制SYS_EN1,SYS_R_WN1,SYS_ADDR即可从SYS_DATA_OUT读出数据。同时可以通过查询SDRAM_BUSY的状态查看读写是否完成。/MODULESDRAM_TOPCLK,RST_N,SDRAM_WR_REQ,10SDRAM_RD_REQ,SDRAM_WR_ACK,SDRAM_RD_ACK,SYS_ADDR,SYS_DATA_IN,SYS_DATA_OUT,SDRAM_CKE,SDRAM_CS_N,SDRAM_RAS_N,SDRAM_CAS_N,SDRAM_WE_N,SDRAM_BA,SDRAM_ADDR,SDRAM_DATA,SDRAM_UDQM,SDRAM_LDQMINPUTCLK/系统时钟，100MHZINPUTRST_N/复位信号，低电平有效INPUTSDRAM_WR_REQ/系统写SDRAM请求信号INPUTSDRAM_RD_REQ/系统读SDRAM请求信号OUTPUTSDRAM_WR_ACK/OUTPUTSDRAM_RD_ACK/INPUT210SYS_ADDR/读写SDRAM时地址暂存器，BIT2120LBANK地址BIT198为行地址，BIT70为列地址INPUT150SYS_DATA_IN/写SDRAM时数据暂存器，4个突发读写字数据，默认为00地址BIT15001地址BIT311610地址BIT473211地址BIT6348OUTPUT150SYS_DATA_OUT/读SDRAM时数据暂存器,格式同上/FPGA与SDRAM硬件接口OUTPUTSDRAM_CKE/SDRAM时钟有效信号OUTPUTSDRAM_CS_N/SDRAM片选信号OUTPUTSDRAM_RAS_N/SDRAM行地址选通脉冲OUTPUTSDRAM_CAS_N/SDRAM列地址选通脉冲11OUTPUTSDRAM_WE_N/SDRAM写允许位OUTPUT10SDRAM_BA/SDRAM的LBANK地址线OUTPUT110SDRAM_ADDR/SDRAM地址总线OUTPUTSDRAM_UDQM/SDRAM高字节屏蔽OUTPUTSDRAM_LDQM/SDRAM低字节屏蔽INOUT150SDRAM_DATA/SDRAM数据总线/SDRAM内部接口WIRE40INIT_STATE/SDRAM初始化寄存器WIRE30WORK_STATE/SDRAM工作状态寄存器WIRE80CNT_CLK/时钟计数REGDQMALWAYSPOSEDGECLKORNEGEDGERST_NIFRST_NDQM1B1ELSEDQM1B0ASSIGNSDRAM_UDQMDQMASSIGNSDRAM_LDQMDQMSDRAM_CTRLMODULE_001/SDRAM状态控制模块CLKCLK,RST_NRST_N,SDRAM_WR_REQSDRAM_WR_REQ,SDRAM_RD_REQSDRAM_RD_REQ,SDRAM_WR_ACKSDRAM_WR_ACK,SDRAM_RD_ACKSDRAM_RD_ACK,INIT_STATEINIT_STATE,WORK_STATEWORK_STATE,CNT_CLKCNT_CLKSDRAM_CMDMODULE_002/SDRAM命令模块CLKCLK,RST_NRST_N,SDRAM_CKESDRAM_CKE,SDRAM_CS_NSDRAM_CS_N,SDRAM_RAS_NSDRAM_RAS_N,SDRAM_CAS_NSDRAM_CAS_N,SDRAM_WE_NSDRAM_WE_N,12SDRAM_BASDRAM_BA,SDRAM_ADDRSDRAM_ADDR,SYS_ADDRSYS_ADDR,INIT_STATEINIT_STATE,WORK_STATEWORK_STATESDRAM_WR_DATAMODULE_003/SDRAM数据读写模块CLKCLK,RST_NRST_N,SDRAM_DATASDRAM_DATA,SYS_DATA_INSYS_DATA_IN,SYS_DATA_OUTSYS_DATA_OUT,WORK_STATEWORK_STATE,CNT_CLKCNT_CLKENDMODULE13附件1大学本科毕业论文（设计）工作程序工作程序及要求完成时间（一）确定题目和指导教师1学院（系）成立毕业论文（设计）领导小组；2学院（系）向教师（具有讲师以上职称或具有研究生学历的助教）分派指导论文（设计）任务，院（系）公布备选题目一览表；3学院（系）召开指导教师和学生参加的毕业论文（设计）布置大会；4学生根据自己的专业兴趣、学术特长选定论文题目，确定指导教师，也可与指导教师协商后确定论文题目；5学院（系）将选题结果汇总成表，报教务处实践教学科备案。每学年第一学期第8周前第一阶段（准备阶段）（二）做好论文开题、写作的准备工作1指导教师向学生传达毕业论文（设计）要求及有关管理规定，师生沟通交流课题任务，使学生正确理解课题，为开题做准备；2学生确定论文题目后，应在指导教师的指导下进行文献检索、实习调研以及实验等论文前期准备工作。每学年第一学期第8周以后（三）做好开题报告教研室组织教师指导学生做好开题报告，院（系）检查开题情况，教务处抽查。每学年第二学期第2周前（四）认真进行毕业论文（设计）指导、检查工作。1指导教师做好指导工作，定期检查学生的工作进度和质量，及时解答和处理学生提出的有关问题；2学院（系）要随时了解、检查论文写作进展情况，及时研究协调处理毕业论文写作过程中的有关问题。每学年第二学期第二阶段（开题及写作阶段）（五）毕业论文中期检查教研室组织中期毕业论文检查工作，做好记录，学生须向指导教师汇报工作进度和工作质量，并填写中期检查表。每学年第二学期第8周（六）指导教师评定毕业论文答辩前一周，学生将毕业论文交指导教师，指导教师需认真审阅，写出评语和评分。（七）评阅老师评阅毕业论文学院（系）或教研室安排有关教师，详细评阅每个学生的毕业论文，给出评分。每学年第二学期第1314周（八）组织答辩学院（系）成立答辩委员会，组织答辩小组对学生进行论文答辩，答辩日程安排通知教务处，并做好答辩记录，给出答辩成绩。每学年第二学期第15周前第三阶段（评审答辩阶段）（九）综合评定成绩学院（系）组织专门人员检查评分标准执行情况，进行成绩汇总和统计；毕业论文成绩及时报送教务处。每学年第二学期第15周前要求阶段14（十）毕业论文归档管理学院（系）收集并整理归档毕业论文有关材料，包括鉴定表（2份）、开题报告（1份）、中期检查表（1份）、评分表（1份）、论文（设计）（1份）及相应电子文档，填写本科生毕业论文（设计）工作总结表，一份交教务处实践教学科。每学年第二学期第16周前（十一）校级优秀毕业论文评选每学年第二学期第17周前注1提前或推延进行毕业论文（设计）的，各阶段要求相同，日程自定；2毕业论文（设计）工作三个阶段时间安排，可根据各专业特点适当调整。附件2大学本科毕业论文（设计）撰写规范一、毕业论文（设计）文本结构毕业论文（设计）主要由8个部分组成封面；目录；题目；中外文摘要；正文；参考文献；谢辞；附录。二、毕业论文（设计）各部分规范1封面封面按学校规定的格式填写，包括论文（设计）题目、作者姓名、指导教师姓名、学科专业等内容。2目录目录由毕业论文（设计）各部分内容的顺序号、名称和页码组成，目次中的内容一般列出二级标题即可。目录应该用“”连接名称与页码。3题目论文（设计）题目要恰当、简明、凝练，能够反映论文的主题及其内容，做到文、题贴切。题目中不使用非规范的缩略词、符号、代号和公式，通常不采用问话的方式。题目所使用的词语应当考虑到有助于选择关键词和编制题录、索引等。题目的中文字数一般不超过20个字，外文题目不超过10个实词，中外文标题应一致，居中编排格式。4中外文摘要及关键词摘要是对毕业论文（设计）内容不加注释和评论的简短陈述。摘要主要是说明研究工作的目的、方法、结果和结论。摘要应具有独立性和自含性，即不阅读全文，就能获得毕业论文（设计）必要的信息，使读者确定有无必要阅读全文。摘要中应用第三人称的方法记述论文的性质和主题，不使用“本文”、15“作者”等作为主语，应采