用在HCL中表示指令PPT课件

SEQCPUImplementation,Whatwewilldiscusstoday?,TheimplementationofasequentialCPU-SEQEveryInstructionfinishedinonecycle.InstructionexecutesinsequentialNotwoinstructionexecuteinparalleloroverlapAnrevisedversionofSEQ-SEQ+ModifythePCUpdatestageofSEQtoshowthedifferencebetweenISAandimplementation,SomeMacros,Instruction,memory,Instruction,memory,PC,increment,PC,increment,CC,CC,ALU,ALU,Data,memory,Datamemory,Fetch,Decode,Execute,Memory,Writeback,icode,ifun,rA,rB,valC,Register,file,Register,file,A,B,M,E,Register,file,Register,file,A,B,M,E,PC,valP,srcA,srcB,dstA,dstB,valA,valB,aluA,aluB,Bch,valE,Addr,Data,valM,PC,valE,newPC,valM,SEQHardwareStructure,StagesFetchReadinstructionfrommemoryDecodeReadprogramregistersExecuteComputevalueoraddressMemoryReadorwritedataWriteBackWriteprogramregistersPCUpdateprogramcounterInstructionFlowReadinstructionataddressspecifiedbyPCProcessthroughstagesUpdateprogramcounter,Instruction,memory,Instruction,memory,PC,increment,PC,increment,CC,CC,ALU,ALU,Data,memory,Data,memory,Fetch,Decode,Execute,Memory,Writeback,icode,ifun,rA,rB,valC,Register,file,Register,file,A,B,M,E,Register,file,Register,file,A,B,M,E,PC,valP,srcA,srcB,dstA,dstB,valA,valB,aluA,aluB,Bch,valE,Addr,Data,valM,PC,valE,valM,newPC,Differencebetweensemanticsandimplementation,ISAEverystagemayupdatesomestates,theseupdatesoccursequentiallySEQAllthestateupdateoperationsoccursimultaneouslyatclockrising(exceptCC),SEQHardware,KeyBlueboxes:predesignedhardwareblocksE.g.,memories,ALUGrayboxes:controllogicDescribeinHCLWhiteovals:labelsforsignalsThicklines:32-bitwordvaluesThinlines:4-8bitvaluesDottedlines:1-bitvalues,FetchLogic,PredefinedBlocksPC:RegistercontainingPCInstructionmemory:Read6bytes(PCtoPC+5)Split:DivideinstructionbyteintoicodeandifunAlign:GetfieldsforrA,rB,andvalC,FetchLogic,ControlLogicInstr.Valid:Isthisinstructionvalid?Needregids:Doesthisinstructionhavearegisterbytes?NeedvalC:Doesthisinstructionhaveaconstantword?,FetchControlLogic,boolneed_regids=icodeinIRRMOVL,IOPL,IPUSHL,IPOPL,IIRMOVL,IRMMOVL,IMRMOVL;boolinstr_valid=icodeinINOP,IHALT,IRRMOVL,IIRMOVL,IRMMOVL,IMRMOVL,IOPL,IJXX,ICALL,IRET,IPUSHL,IPOPL;,DecodeicodeinIPOPL,IRET:RESP;1:RNONE;#Dontneedregister;,EDestination,intdstE=icodeinIRRMOVL,IIRMOVL,IOPL:rB;icodeinIPUSHL,IPOPL,ICALL,IRET:RESP;1:RNONE;#Dontneedregister;,ExecuteLogic,UnitsALUImplements4requiredfunctionsGeneratesconditioncodevaluesCCRegisterwith3conditioncodebitsbcondComputesbranchflagControlLogicSetCC:Shouldconditioncoderegisterbeloaded?ALUA:InputAtoALUALUB:InputBtoALUALUfun:WhatfunctionshouldALUcompute?,ALUAInput,intaluA=icodeinIRRMOVL,IOPL:valA;icodeinIIRMOVL,IRMMOVL,IMRMOVL:valC;icodeinICALL,IPUSHL:-4;icodeinIRET,IPOPL:4;#OtherinstructionsdontneedALU;,ALUOperation,intalufun=icode=IOPL:ifun;1:ALUADD;,ConditionSet,Boolset_cc=icodeinIOPL;WewillnotdiscussthedetailofBcondThoughitisalsoacontrolunit,MemoryLogic,MemoryReadsorwritesmemorywordControlLogicMem.read:shouldwordberead?Mem.write:shouldwordbewritten?Mem.addr.:SelectaddressMem.data.:Selectdata,MemoryAddress,intmem_addr=icodeinIRMMOVL,IPUSHL,ICALL,IMRMOVL:valE;icodeinIPOPL,IRET:valA;#Otherinstructionsdontneedaddress;,MemoryRead,boolmem_read=icodeinIMRMOVL,IPOPL,IRET;boolmem_write=icodeinIRMMOVL,IPUSHL,ICALL;,PCUpdateLogic,NewPCSelectnextvalueofPC,PCUpdate,intnew_pc=icode=ICALL:valC;icode=IJXX,SEQHardware(Review),StagesoccurinsequenceOneoperationinprocessatatime,SEQ+Hardware,StillsequentialimplementationReorderPCstagetoputatbeginningPCStageTaskistoselectPCforcurrentinstructionBasedonresultscomputedbypreviousinstructionProcessorStatePCisnolongerstoredinregisterBut,candeterminePCbasedonotherstoredinformation,PCComputation,Intpc=pIcode=ICALL:pValC;pIcode=IJXX,SEQSummary,ImplementationExpresseveryinstructionasseriesofsimplestepsFollowsamegeneralflowforeachinstructiontypeAssembleregisters,memories,predesignedcombinationalblocksConnect