美图Meitu M6线路原理图

5 5 4 4 3 3 2 2 1 1 DD CC BB AA Note: 10-5 Note: 10-2 Remote sense trace with GNDshielding to PMIC (Differential) Schematic design notice of 10_BB_POWER_1 page. Note 10-1: Note: 10-4 Note: 10-3 Note 10-2: Note 10-3: Note 10-4: Note 10-5: VCORE_1 remote sense must be close to MT6795s AG13 ball. Differential pair of DVFS1 remote sense must be close to MT6795s Y10 ball. Differential pair of DVDD_MD remote sense must be close to MT6795s K22 ball. VDRAM remote sense must be close to MT6795s A32 ball or be placed to the farest power ball of VDRAM from MT6332 point of view. Differential pair of GPU remote sense must be close to MT6795s J8 ball. Note: 10-1 DVDD_SRAM1 DVDD_DVFS1 DVDD_DVFS1 VCORE1_PMU DVDD_DVFS1 VSRAM_VDVFS2_PMU D_GND VGPU_PMU D_GND DVDD_DVFS1 VDRAM_PMU D_GND D_GND D_GND DVDD_MD VCORE1_PMU D_GND VIO18_PMU D_GND DVDD_GPU_PMIC_FB20 VDRAM_PMIC_FB21 DVDD_DRAM_GND21 DVDD_GPU_GND20 DVDD_MD_PMIC_FB21 DVDD_MD_GND21 DVDD_DVFS_1_PMIC_FB24 DVDD_DVFS1_GND24 DVDD_DVFS124 VCORE1_PMU_FB20 Title Size Sheet Name Rev Date:Sheetof ENGINEER: 厦门美图公司厦门美图公司 BB_POWER_1 3.0.0 VIENNA A2 1099 Friday, August 07, 2015 Huanggai Title Size Sheet Name Rev Date:Sheetof ENGINEER: 厦门美图公司厦门美图公司 BB_POWER_1 3.0.0 VIENNA A2 1099 Friday, August 07, 2015 Huanggai Title Size Sheet Name Rev Date:Sheetof ENGINEER: 厦门美图公司厦门美图公司 BB_POWER_1 3.0.0 VIENNA A2 1099 Friday, August 07, 2015 Huanggai C1028CC0201N C1154CC0201N C1015CC0201N C1009CC0201N C1016CC0201N C1033CC0201N C1082CC0201N R1001RC0402L C1026CC0603L C1092CC0201N C1011CC0201N R1002 RC0402L C1030CC0201N C1078CC0201N C1005CC0603L C1093CC0201N C1089CC0201N C1032CC0201N C1157CC0201N C1073CC0402L C1152CC0201N C1048CC0201N C1162CC0201N C1046CC0201N C1040CC0201N C1075CC0402L C1084CC0201N C1014CC0201N C1022CC0201N C1056CC0201N C1150CC0201N C1076CC0201N C1099CC0201N C1079CC0201N SH1007 12 C1161CC0201N C1158CC0201N C1066CC0402L C1021CC0201N C1007CC0603L C1098CC0201N C1034CC0201N SH1003 12 C1086CC0201N C1025CC0201N C1159CC0201N C1018CC0201N C1087CC0402L C1151CC0201N C1065CC0603L C1010CC0201N C1094CC0201N C1096CC0201N C1013CC0201N C1050CC0201N C1042CC0201N C1019CC0201N C1083CC0603L C1072CC0201N C1001CC0603L SH1006 12 SH1009 12 C1036CC0201N C1160CC0201N C1088CC0201N C1080CC0201N SH1004 12 C1012CC0201N C1069CC0201N GPU VCCK VDDQ MT6795-MWFPOP-852P SRAM DVFS1 VDD1 MD U1001E DVDD_CORE1_17 T22 DVDD_CORE1_18 T23 DVDD_CORE1_19 T24 DVDD_CORE1_21 U22 DVDD_CORE1_22 U23 DVDD_CORE1_23 U24 DVDD_CORE1_24 V23 DVDD_CORE1_25 V24 DVDD_CORE1_26 W23 DVDD_CORE1_27 W24 DVDD_CORE1_28 Y23 DVDD_CORE1_29 Y24 DVDD_CORE1_32 AA23 DVDD_CORE1_33 AA24 DVDD_CORE1_34 AB23 DVDD_CORE1_35 AB24 DVDD_CORE1_38 AC23 DVDD_CORE1_39 AC24 DVDD_CORE1_40 AD23 DVDD_CORE1_41 AD24 DVDD_CORE1_49 AE22 DVDD_CORE1_50 AE23 DVDD_CORE1_51 AE24 DVDD_CORE1_55 AF14 DVDD_CORE1_58 AF17 DVDD_CORE1_59 AF18 DVDD_CORE1_60 AF19 DVDD_CORE1_61 AF20 DVDD_CORE1_62 AF21 DVDD_CORE1_63 AF22 DVDD_CORE1_64 AF23 DVDD_CORE1_65 AF24 DVDD_CORE1_10 M18 DVDD_CORE1_16 T11 DVDD_CORE1_30 Y25 DVDD_SRAM1_0 Y15 DVDD_SRAM1_1 AA15 DVDD_SRAM1_3 AE19 DVDD_SRAM1_4 AE20 VDD1_0 B32 VDD1_1 C2 VDD1_2 C3 VDD1_3 M34 VDD1_4 AH34 VDD1_5 AM3 VDD1_6 AP12 VDD1_7 AP28 VDDQ_0 A7 VDDQ_1 A10 VDDQ_2 A13 VDDQ_3 A16 VDDQ_4 A19 VDDQ_5 A23 VDDQ_6 A26 VDDQ_7 A32 VDDQ_8 B3 VDDQ_9 C1 VDDQ_10 C34 VDDQ_11 J1 VDDQ_12 K34 VDDQ_13 M1 VDDQ_14 P34 VDDQ_15 T1 VDDQ_16 Y34 VDDQ_17 AB1 VDDQ_18 AF34 VDDQ_19 AH1 VDDQ_20 AJ34 VDDQ_21 AL1 VDDQ_22 AP3 VDDQ_23 AP6 VDDQ_24 AP11 VDDQ_25 AP14 VDDQ_26 AP17 VDDQ_27 AP20 VDDQ_28 AP24 VDDQ_29 AP27 DVDD_DVFS1_9 V13 DVDD_DVFS1_10 W9 DVDD_DVFS1_11 W10 DVDD_DVFS1_12 W11 DVDD_DVFS1_13 W12 DVDD_DVFS1_14 W13 DVDD_DVFS1_15 W14 DVDD_DVFS1_16 Y10 DVDD_DVFS1_17 Y13 DVDD_DVFS1_18 Y14 DVDD_DVFS1_21 AA13 DVDD_DVFS1_25 AB11 DVDD_DVFS1_26 AB13 DVDD_DVFS1_33 AC9 DVDD_DVFS1_34 AC10 DVDD_DVFS1_35 AC11 DVDD_DVFS1_36 AC12 DVDD_DVFS1_28 AB17 DVDD_DVFS1_29 AB18 DVDD_DVFS1_30 AB19 DVDD_DVFS1_31 AB20 DVDD_DVFS1_32 AB21 DVDD_DVFS1_41 AC20 DVDD_DVFS1_42 AC21 DVDD_DVFS1_49 AD20 DVDD_DVFS1_48 AD19 DVDD_GPU_0 J8 DVDD_GPU_1 J9 DVDD_GPU_2 J10 DVDD_GPU_3 J11 DVDD_GPU_4 J13 DVDD_GPU_5 J15 DVDD_GPU_9 L8 DVDD_GPU_10 L9 DVDD_GPU_11 L10 DVDD_GPU_17 L16 DVDD_GPU_23 M16 DVDD_GPU_6 K11 DVDD_GPU_7 K13 DVDD_GPU_8 K15 DVDD_GPU_12 L11 DVDD_GPU_13 L12 DVDD_GPU_14 L13 DVDD_GPU_15 L14 DVDD_GPU_16 L15 DVDD_GPU_18 M11 DVDD_GPU_19 M12 DVDD_GPU_20 M13 DVDD_GPU_21 M14 DVDD_GPU_22 M15 DVDD_GPU_24 N11 DVDD_GPU_25 N12 DVDD_CORE1_53 AF12 DVDD_CORE1_15 T10 DVDD_DVFS1_0 U8 DVDD_DVFS1_1 U9 DVDD_DVFS1_2 U10 DVDD_DVFS1_3 U11 DVDD_DVFS1_4 U12 DVDD_DVFS1_5 U13 DVDD_DVFS1_6 V10 DVDD_DVFS1_7 V11 DVDD_DVFS1_8 V12 DVDD_DVFS1_19 AA9 DVDD_DVFS1_20 AA10 DVDD_DVFS1_24 AB10 DVDD_DVFS1_27 AB14 DVDD_DVFS1_37 AC13 DVDD_DVFS1_38 AC14 DVDD_DVFS1_43 AD11 DVDD_DVFS1_44 AD12 DVDD_DVFS1_40 AC19 DVDD_SRAM1_2 AB15 DVDD_DVFS1_22 AA17 DVDD_DVFS1_23 AA19 DVDD_CORE1_36 AB25 DVDD_CORE1_37 AB26 DVDD_DVFS1_39 AC17 DVDD_DVFS1_45 AD15 DVDD_DVFS1_46 AD16 DVDD_DVFS1_47 AD17 DVDD_CORE1_9 L27 DVDD_CORE1_7 K27 DVDD_CORE1_0 J18 DVDD_CORE1_1 J19 DVDD_CORE1_2 J20 DVDD_CORE1_3 J21 DVDD_CORE1_4 J22 DVDD_CORE1_31 Y26 DVDD_CORE1_68 AG13 DVDD_CORE1_69 AG15 DVDD_CORE1_70 AG18 DVDD_CORE1_72 AH11 DVDD_CORE1_42 AD25 DVDD_CORE1_43 AD26 DVDD_CORE1_44 AD27 DVDD_CORE1_47 AE10 DVDD_CORE1_48 AE11 DVDD_CORE1_66 AF25 DVDD_CORE1_45 AE8 DVDD_CORE1_46 AE9 DVDD_CORE1_54 AF13 DVDD_CORE1_52 AF11 DVDD_MD_0 K21 DVDD_MD_1 K22 DVDD_MD_2 L22 DVDD_MD_3 L23 DVDD_MD_4 M21 DVDD_MD_5 M22 DVDD_MD_6 M23 DVDD_CORE1_11 M27 DVDD_MD_7 N22 DVDD_MD_8 N23 DVDD_MD_17 N24 DVDD_MD_9 N25 DVDD_CORE1_20 T27 DVDD_CORE1_13 P27 DVDD_CORE1_14 R27 DVDD_CORE1_12 N27 DVDD_CORE1_73 AH13 DVDD_CORE1_74 AH15 DVDD_CORE1_75 AH18 DVDD_CORE1_76 AH25 DVDD_CORE1_67 AG11 DVDD_CORE1_71 AG25 DVDD_MD_16 R25 DVDD_MD_15 R24 DVDD_MD_14 R23 DVDD_MD_13 R22 DVDD_MD_12 P23 DVDD_MD_11 P22 DVDD_MD_10 P21 DVDD_CORE1_8 L18 DVDD_CORE1_6 K26 DVDD_CORE1_5 K18 DVDD_CORE1_56 AF15 DVDD_CORE1_57 AF16 C1085CC0603L C1024CC0201N C1090CC0201N C1035CC0201N C1070CC0201N SH1001 12 C1153CC0201N C1156CC0201N C1002CC0603L C1052CC0201N C1091CC0201N C1095CC0201N C1071CC0201N SH1005 12 C1004CC0603L C1017CC0201N C1031CC0201N SH1002 12 C1006CC0603L C1054CC0201N C1077CC0402L SH1008 12 C1023CC0201N C1038CC0201N C1003CC0603L C1020CC0201N C1074CC0201N C1027CC0603L C1044CC0201N C1155CC0201N C1081CC0201N C1097CC0201N 5 5 4 4 3 3 2 2 1 1 DD CC BB AA Connect AVDD33_USB_P1 (B4 ball) to VSIM1_PMU for IC-USB / Samrt card application. Schematic design notice of 11_BB_POWER page. Note 11-3: Connect AVDD33_USB_P1 (B4 ball) to VUSB33_PMU for USB application. Note 11-1: AVDD28_DAC (Y33 ball) must be powered by VTCXO_1_PMU. Connect VCC18IO_CMR (E26 ball) to VIO18_PMU since I2C-2 I/O power is powered by VCC18IO_CMR. Note 11-2: Reserve 0.1uF decoupling cap in VCC18IO_DPI for MHL. Note 11-4: 6mil 6mil 6mil 12mil 12mil 6mil 12mil 6mil 6mil 6mil 6mil 6mil 6mil 6mil 6mil Note: 11-5 Note: 11-2 12mil Note: 11-4 Note: 11-3 6mil 6mil 6mil 6mil 6mil 6mil 6mil Note: 11-1 D_GND D_GND VIO18_PMU VIO18_PMU VSIM1_PMU VSIM2_PMU D_GND VIO18_PMU VIO18_PMU D_GND VIO18_PMU D_GNDD_GND VIO18_PMU VIO18_PMU VIO18_PMU VMC_PMU D_GNDD_GNDD_GND VIO18_PMU VIO18_PMU VIO18_PMU D_GND VUSB33_PMU VUSB10_PMU VIO18_PMU D_GNDD_GND D_GND D_GND D_GND VTCXO_1_PMU VIO18_PMU D_GNDD_GND D_GND D_GNDD_GND D_GND VIO18_PMU VUSB33_PMU Title Size Sheet Name Rev Date:Sheetof ENGINEER: 厦门美图公司厦门美图公司 BB_POWER_2 3.0.0 VIENNA A2 1199 Friday, August 07, 2015 Huanggai Title Size Sheet Name Rev Date:Sheetof ENGINEER: 厦门美图公司厦门美图公司 BB_POWER_2 3.0.0 VIENNA A2 1199 Friday, August 07, 2015 Huanggai Title Size Sheet Name Rev Date:Sheetof ENGINEER: 厦门美图公司厦门美图公司 BB_POWER_2 3.0.0 VIENNA A2 1199 Friday, August 07, 2015 Huanggai C1101 CC0201N PERI_DAVDD & MD_A MT6795-MWFPOP-852P PLL PERI_A / MIPI PERI_A / USB U1001F AVDD18_PLLGP U32 AVDD18_MD_0 R31 AVDD18_MD_1 R32 AVDD18_AP V32 AVDD28_DAC Y33 AVSS18_PLLGP P33 AVSS18_MD_0 R33 AVSS18_MD_1 W31 AVSS18_MD_2 W32 AVDD18_MEMPLL_A D34 AVDD18_MEMPLL_B AK1 AVDD18_MEMPLLPOP AG26 AVSS18_MEMPLL_A C33 AVSS18_MEMPLL_B AL2 VCC28IO_BPI D32 VCC28_EMD G1 VCC18IO_BPI F32 VCC18IO_MD1 AM33 VCC18IO_CMR E26 VCC18IO_CONN F13 VCC18IO_BPI_1 N32 VCC18IO_BPI_2 AM34 VCC18IO_0 K1 VCC18IO_1 N6 VCC18IO_EINT H3 VCC18IO_MC0 W5 VCC18IO_MC1 R3 VCC33IO_MC1 N1 VCC18IO_MC2 AP25 VCC33IO_MC2 AM26 VCC18IO_MC3 C11 VCC18IO_SIM_0 AM5 VCC18IO_SIM_1 AM6 VCC33IO_SIM1 AK8 VCC33IO_SIM2 AK5 VCC18IO_DPI AC5 VCC18IO_I2S AF5 VCC18IO_UART AM10 AVDD18_MIPITX1 AN23 AVDD18_MIPITX2 AN19 AVDD18_MIPIRX0 C16 AVDD18_MIPIRX1 E20 AVDD18_MIPIRX2 E25 AVSS18_MIPITX_1 AK23 AVSS18_MIPITX_2 AP18 AVSS18_MIPIRX_0 C23 AVSS18_MIPIRX_1 E19 AVSS18_MIPIRX_2 E24 AVDD10_SSUSB B9 AVDD18_SSUSB A8 AVDD18_USB_P0 F7 AVDD33_USB_P0 C6 AVDD18_USB_P1 C5 AVDD33_USB_P1 B4 AVSS10_SSUSB_0 E9 AVSS10_SSUSB_1 E10 AVSS33_USB_P0 B7 AVSS33_USB_P1 C4 VCC18IO_3 AC7 AVSS18_MEMPLLPOP AG27 AVDD18_ARMPLL W15 AVSS18_ARMPLL W16 C1106 CC0201N C1103 CC0201N C1114 CC0201N C1108 CC0201N C1102 CC0201N C1115 CC0201N C1104 CC0201N GND MT6795-MWFPOP-852P GND U1001G DVSS0 A14 DVSS1 A28 DVSS2 A31 DVSS3 B2 DVSS4 B10 DVSS5 B33 DVSS6 C7 DVSS7 C12 DVSS8 C17 DVSS9 C20 DVSS10 D11 DVSS11 D25 DVSS12 E15 DVSS13 E30 DVSS14 F26 DVSS15 G3 DVSS16 G32 DVSS17 H6 DVSS18 J12 DVSS19 J14 DVSS20 J16 DVSS21 J17 DVSS22 J23 DVSS23 J34 DVSS25 K9 DVSS26 K10 DVSS27 K12 DVSS28 K14 DVSS29 K16 DVSS30 K17 DVSS31 K19 DVSS32 K20 DVSS33 K23 DVSS34 K24 DVSS35 M4 DVSS36 L5 DVSS37 L17 DVSS38 L19 DVSS39 L20 DVSS40 L21 DVSS41 L24 DVSS42 L25 DVSS43 L26 DVSS45 M9 DVSS46 M10 DVSS47 M17 DVSS48 M19 DVSS49 M20 DVSS50 M24 DVSS51 M25 DVSS52 M26 DVSS54 N9 DVSS55 N10 DVSS56 N13 DVSS57 N14 DVSS58 N15 DVSS132 V20 DVSS133 V21 DVSS134 V22 DVSS135 V25 DVSS136 V26 DVSS140 W19 DVSS141 W20 DVSS142 W21 DVSS143 W22 DVSS144 W25 DVSS145 W26 DVSS147 Y3 DVSS148 Y9 DVSS149 Y11 DVSS151 Y16 DVSS152 Y17 DVSS153 Y18 DVSS154 Y19 DVSS157 Y22 DVSS159 AA11 DVSS160 AA12 DVSS162 AA16 DVSS163 AA18 DVSS166 AA22 DVSS168 AA26 DVSS170 AA33 DVSS171 AB9 DVSS173 AB16 DVSS174 AB22 DVSS176 AC6 DVSS177 AC15 DVSS179 AC18 DVSS180 AC22 DVSS181 AC25 DVSS182 AC26 DVSS184 AD1 DVSS185 AD9 DVSS186 AD10 DVSS187 AD13 DVSS188 AD14 DVSS190 AD21 DVSS191 AD22 DVSS200 AE25 DVSS201 AE26 DVSS203 AF26 DVSS205 AF33 DVSS206 AG5 DVSS217 AH10 DVSS223 AJ24 DVSS224 AK6 DVSS225 AK29 DVSS226 AK30 DVSS227 AL3 DVSS228 AL7 DVSS229 AL34 DVSS230 AM7 DVSS231 AM9 DVSS232 AM14 DVSS233 AM17 DVSS234 AM20 DVSS235 AM23 DVSS236 AM27 DVSS237 AM30 DVSS238 AN2 DVSS240 AP5 DVSS24 K8 DVSS44 M8 DVSS53 N8 DVSS59 N16 DVSS60 N17 DVSS61 N18 DVSS62 N19 DVSS63 N20 DVSS64 N21 DVSS65 N26 DVSS66 N33 DVSS67 N34 DVSS68 P6 DVSS70 P9 DVSS71 P10 DVSS72 P11 DVSS73 P12 DVSS74 P13 DVSS75 P14 DVSS76 P15 DVSS77 P16 DVSS78 P17 DVSS79 P18 DVSS80 P19 DVSS81 P20 DVSS82 P24 DVSS83 P25 DVSS84 P26 DVSS86 R9 DVSS87 R10 DVSS88 R11 DVSS89 R12 DVSS90 R13 DVSS91 R14 DVSS92 R15 DVSS93 R16 DVSS94 R17 DVSS95 R18 DVSS96 R19 DVSS97 R20 DVSS98 R21 DVSS99 R26 DVSS69 P8 DVSS85 R8 DVSS101 T9 DVSS102 T12 DVSS103 T13 DVSS104 T14 DVSS105 T15 DVSS106 T16 DVSS107 T17 DVSS108 T18 DVSS109 T19 DVSS110 T20 DVSS111 T21 DVSS112 T25 DVSS113 T26 DVSS100 T8 DVSS114 U6 DVSS117 U16 DVSS118 U17 DVSS119 U18 DVSS120 U19 DVSS121 U20 DVSS122 U21 DVSS123 U25 DVSS124 U26 DVSS131 V19 DVSS150 Y12 DVSS155 Y20 DVSS156 Y21 DVSS164 AA20 DVSS165 AA21 DVSS178 AC16 DVSS189 AD18 DVSS192 AE12 DVSS193 AE13 DVSS198 AE18 DVSS199 AE21 DVSS216 AG24 DVSS215 AG23 DVSS214 AG22 DVSS213 AG21 DVSS212 AG20 DVSS211 AG19 DVSS210 AG17 DVSS209 AG16 DVSS208 AG14 DVSS207 AG10 DVSS218 AH12 DVSS239 AN9 DVSS172 AB12 DVSS194 AE14 DVSS195 AE15 DVSS196 AE16 DVSS197 AE17 DVSS202 AE27 DVSS204 AF27 DVSS219 AH14 DVSS220 AH16 DVSS221 AH17 DVSS222 AH24 DVSS115 U14 DVSS116 U15 DVSS125 U27 DVSS137 V27 DVSS158 Y27 DVSS138 W17 DVSS139 W18 DVSS146 W27 DVSS167 AA25 DVSS169 AA27 DVSS161 AA14 DVSS175 AB27 DVSS183 AC27 DVSS126 V8 DVSS127 V9 DVSS128 V14 DVSS129 V17 DVSS130 V18 C1113 CC0201N C1109 CC0201N C1116 C1111 CC0201N C1112 CC0201N C1107 CC0201N C1110 CC0201N C1105 CC0201N 5 5 4 4 3 3 2 2 1 1 DD CC BB AA Note: 12-1 Close to BB IC. Note: 12-2 Note 12-1: Schematic design notice of 11_BB_11 page. Note 12-2: The BPI_BUS0BPI_BUS9 are capable of 2.8V I/O operation. Apply 1.8V to DVDD18_EFUSE (AK24) for eFuse programming. Note 12-3: The de-coupling cap. of DRAM VREF have to be placed as close to BB as possible. Note: 12-3 Note: 12-4 SRCLKENAI2 features watch dog reset output to reset 4-phase buck. Note 12-4: R1207 BOM option: R1207 = 0R when BOM option of U2401 is DA9210. R1207 = NC when BOM option of U2401 is 2nd source. 1% 1% 1% 1% 1% HW_ID JTRST_B JTCK JTDI JTMS AUX_IN0_NTCAP TEMPERATURE MIPI0_SCLK MIPI0_SDATA MIPI1_SDATA MIPI1_SCLK AUX_IN2_NTCLTE B7 PA TEMPERATURE JTDO AUX_IN0_NTC D_GND D_GND D_GND D_GNDD_GND D_GND D_GND D_GNDD_GNDD_GNDD_GND DDR_VREF DDR_VREF VDRAM_PMU D_GND VIO18_PMU D_GND VIO18_PMU D_GND WATCHDOG20,21,24 SRCLKENA020,21,24,31 SRCLKENA120,21 RTC32K1V820,21 LCM_PWM61 PWRAP_SPI0_CSN20,21 PWRAP_SPI0_CK20,21 LTE_RFIC0_BSI_CK31 LTE_RFIC0_BSI_EN31 LTE_LTEX26M_IN 31 LTE_TX_BBIP 31 LTE_TX_BBIN 31 PWRAP_SPI0_MO20,21 PWRAP_SPI0_MI20,21 SYSRSTB20 LTE_TX_BBQP 31 LTE_TX_BBQN 31 LTE_RX1_BBIP 31 LTE_RX1_BBIN 31 LTE_RX1_BBQP 31 LTE_RX1_BBQN 31 LTE_RX2_BBIP 31 LTE_RX2_BBIN 31 LTE_RX2_BBQP 31 LTE_RX2_BBQN 31 LTE_RFIC0_BSI_D231 LTE_RFIC0_BSI_D131 LTE_RFIC0_BSI_D031 AUD_DAT_MISO_120 INT_SIM123 SIM1_CARD_SRST23 SIM1_CARD_SCLK23 SIM1_CARD_SIO23 SRCLKENAI51 LTE_BPI_OUT1334 MIPI0_SCLK 32 MIPI1_SCLK 33 MIPI1_SDATA 33 MIPI0_SDATA 32 LTE_APC1 32 AUD_DAT_MOSI_120 AUD_DAT_MOSI_220 AUD_DAT_MISO_220 LTE_BPI_OUT433 AUD_CLK_MOSI20 LTE_TXBPI31 LTE_BPI_OUT1833 AUX_IN2_NTC 32 EXT_4P_PMU_EN24 HW_ID113 HW_ID213 HW_ID313 LTE_BPI_BUS323 LTE_BPI_BUS223 LTE_BPI_OUT133 LTE_BPI_OUT1434 LTE_BPI_OUT1634 LTE_BPI_OUT1534 Title Size Sheet Name Rev Date:Sheetof ENGINEER: 厦门美图公司厦门美图公司 BB_1 3.0.0 VIENNA A2 1299 Friday, August 07, 2015 Huanggai Title Size Sheet Name Rev Date:Sheetof ENGINEER: 厦门美图公司厦门美图公司 BB_1 3.0.0 VIENNA A2 1299 Friday, August 07, 2015 Huanggai Title Size Sheet Name Rev Date:Sheetof ENGINEER: 厦门美图公司厦门美图公司 BB_1 3.0.0 VIENNA A2 1299 Friday, August 07, 2015 Huanggai C1213 CC0201N C1217 CC0201N C1209 CC0201N R1251 C1218 CC0201N Misc PLLs Test Pin DRAM_IFPMU_IF NC JTAG MT6795-MWFPOP-852P U1001A SYSRSTB H2 WATCHDOG G4 SRCLKENA0 H5 SRCLKENA1 J2 SRCLKENAI J5 SRCLKENAI2 H4 RTC32K_CK K5 PWRAP_SPI0_CSN L3 PWRAP_SPI0_CK M5 PWRAP_SPI0_MO N5 PWRAP_SPI0_MI M6 AUD_CLK_MOSI M3 AUD_DAT_MOSI L2 AUD_DAT_MISO M2 ANC_DAT_OUT K4 ANC_DAT_IN L4 DISP_PWM0 K2 TP_MEMPLLPOP AP33 TN_MEMPLLPOP AN34 TP_MEMPLL_A B34 TN_MEMPLL_A A33 TP_MEMPLL_B AP2 TN_MEMPLL_B AN1 JTRST_B AM11 JTCK AN12 JTDO AL11 JTDI AL12 JTMS AK13 DVDD18_EFUSE AK24 TESTMODE R5 NC1 A1 NC2 A2 NC3 A34 NC4 B1 NC5 AP1 NC6 AP34 ZQ0_A AN14 ZQ1_A AN13 ZQ0_B AG33 ZQ1_B AH33 EXTDN_A J29 DDRVPOP1 AH27 DDRVPOP2 AH28 DDRVPOP3 AH29 DDRV_A_0 H24 DDRV_A_1 H26 DDRV_A_2 H28 DDRV_A_3 J24 DDRV_A_4 J26 DDRV_A_5 J28 DDRV_B_0 AF9 DDRV_B_1 AG9 DDRV_B_2 AH9 DDRV_B_3 AJ9 DDRV_B_4 AJ10 DDRV_B_5 AJ11 VREF_A H30 VREF(CA)_A AN18 VREF(DQ)_A A22 VREF_B AK9 VREF(CA)_B AA34 VREF(DQ)_B W1 TP_ARMPLL V15 TN_ARMPLL V16 VBIASNPOP AH26 VBIASN1_A K25 VBIASN1_B AG12 C1207 CC0201N BPI - W/G SIM BPI - L AUX IN MT6795-MWFPOP-852P ABB_IF RFI_C REF POWER MISC BSI U1001B SIM1_SCLK AN7 SIM1_SIO AN8 SIM1_SRST AP8 INT_SIM1 AH4 SIM2_SCLK AL6 SIM2_SIO AN6 SIM2_SRST AL5 INT_SIM2 AH3 BPI_OUT14 H31 BPI_OUT13 G31 BPI_OUT12 H33 BPI_OUT11 G33 BPI_OUT10 G34 BPI_BUS9 F34 BPI_BUS8 F33 BPI_BUS7 E33 BPI_BUS6 D33 BPI_BUS5 F31 BPI_BUS4 E31 BPI_BUS3 D31 BPI_BUS2 C32 BPI_BUS1 C31 BPI_BUS0 B31 RFIC0_BSI_EN M33 RFIC0_BSI_CK L32 RFIC0_BSI_D2 M32 RFIC0_BSI_D1 L33 RFIC0_BSI_D0 L31 TD_TXBPI K33 RFIC1_BSI_EN K32 RFIC1_BSI_CK J33 RFIC1_BSI_D2 K31 RFIC1_BSI_D1 K30 RFIC1_BSI_D0 J30 LTE_TXBPI AL33 PAVM1 AL29 PAVM0 AL30 BPI_OUT25 AP30 BPI_OUT24 AN30 BPI_OUT23 AP31 BPI_OUT22 AN31 BPI_OUT21 AM31 BPI_OUT20 AN32 BPI_OUT19 AM32 BPI_OUT18 AN33 BPI_OUT17 AL32 BPI_OUT16 AL31 BPI_OUT15 AK31 TDX26M_IN W28 TD_TX_BBIP V34 TD_TX_BBIN W33 TD_TX_BBQP V33 TD_TX_BBQN U33 TD_RX_BBIP R30 TD_RX_BBIN P30 TD_RX_BBQP M30 TD_RX_BBQN N30 APC Y31 APC2 Y32 LTEX26M_IN AA28 LTE_TX_BBIP AE30 LTE_TX_BBIN AD30 LTE_TX_BBQP AB30 LTE_TX_BBQN AC30 LTE_RX1_BBIP AD34 LTE_RX1_BBIN AD33 LTE_RX1_BBQP AE32 LTE_RX1_BBQN AD32 LTE_RX2_BBIP AB32 LTE_RX2_BBIN AC32 LTE_RX2_BBQP AC33 LTE_RX2_BBQN AC34 ET_P AG31 ET_N AG32 MISC_BSI_CS0B AH31 MISC_BSI_CS1B AJ31 MISC_BSI_CK AJ33 MISC_BSI_DO AH32 MISC_BSI_DI AK33 AUXIN2 V31 AUXIN1 T31 AUXIN0 U31 REFP T34 REFN T33 TP1214TEST60 R1201 rc0201n R1252 R1204rc0201n C1215 CC0201N R1208 rc0201n TP1212TEST60 C1203CC0402L R1202rc0201n TP1215TEST60 TP1217 TEST40 C1201CC0402L C1210 CC0201N R1250 rc0201n C1212 CC0201N TP1218 TEST40 C1204 CC0201N C1208 CC0201N R1205rc0201n R1225 rc0201n R1207 rc0201n TP1216TEST60 C1205CC0201N R1226 rc0201n C1214 CC0201N C1216 CC0201N C1202CC0201N RT1201 R1203rc0201n TP1213TEST60 R1224 R1230 1% rc0201n C1206 CC0402L 5 5 4 4 3 3 2 2 1 1 DD CC BB AA Schematic design notice of 12_BB_2 page. Note: 13-1 Note 13-1: Connect USB_VBUS_P0 (C8 ball) pin to GND since USB OTG B-Valid detection has implemented by MT6332s ADC. Note: 13-2 Note 13-2: GPIO103 is dedicated for DA9210 4-phase buck control. SSUSB_VRT USB_VRT_P1 MSDC0_DAT7 MSDC0_DAT6 MSDC0_DAT5 MSDC0_DAT4 MSDC0_DAT3 MSDC0_DAT2 MSDC0_DAT1 MSDC0_DAT0 MSDC3_DAT3 MSDC3_DAT2 MSDC3_DAT1 MSDC3_DAT0 MIPI_VRT_A MIPI_VRT EINT6CTP - EINT EINT0HP - EINT EINT46630 - BGF - INTB EINT56630 - WIFI - INTB GPIO1006630 - GPS LNA EN EINT74-PHASE-BUCK-INT EINT8EINT- ALS / PS EINT11 GPIO1034-PHASE-BUCK_CTRL GPIO102CTP - RST GPIO1016630 - PMU EN GPIO105SENSOR - INT - A+GYRO EINT1MC1 - INSI EINT3NFC - IRQ GPIO104NFC - EINT UTXD3 URXD3 D_GND D_GND VIO18_PMU VIO18_PMU D_GNDD_GND D_GND VIO18_PMU VIO18_PMU ISP_VDDEST RCP63 RCN63 RDP063 RDN063 RDP163 RDN163 RDP263 RDN263 RDP363 RDN363 CHD_DP_P