各种触发器的VHDL程序

题目：写出带异步复位边沿（下降沿）JK触发器的VHDL程序：LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY jk1 isPORT (clk,R,S : INSTD_LOGIC; j,k: INSTD_LOGIC; q,qn : OUTSTD_LOGIC);END jk1;ARCHITECTURE one OF jk1 IS SIGNAL q_s : STD_LOGIC;BEGIN PROCESS (R,S,clk,j,k) BEGIN IF (R=1 AND S=0) THEN q_s=0; ELSIF(R=0 AND S=1) THEN q_s=1; ELSIF clkEVENT AND clk=0 THEN IF (J=0 AND k=0) THEN q_s= q_s; ELSIF (J=0 AND k=1)THEN q_s=0; ELSIF (J=1 AND k=0)THEN q_s=1; ELSIF (J=1 AND k=1) THEN q_s=NOT q_s; END IF; END IF;END PROCESS;q=q_s;qn=not q_s;END one;基本RS触发器entity rsff is port(r,s:in std_logic; q,qb:out std_logic);end rsff;architecture rtl of rsff is signal q_temp,qb_temp:std_logic;beginprocess(r,s) begin if(s=1 and r=0)then q_temp=1; qb_temp=0; elsif(s=0 and r=1)then q_temp=0; qb_temp=1; else q_temp=q_temp; qb_temp=qb_temp; end if; end process;q=q_temp;qb=qb_temp;end rtl;. 同步RS触发器 library ieee;use ieee.std_logic_1164.all;entity synrsff is port(clk,r,s:in std_logic; q,qb:out std_logic);end synrsff;architecture rtl of synrsff is signal q_temp,qb_temp:std_logic;begin process(clk,r,s) begin if(clk=1)then if(s=1 and r=0)thenq_temp=1; qb_temp=0; elsif(s=0 and r=1)then q_temp=0; qb_temp=1; else q_temp=q_temp; qb_temp=qb_temp; end if; else q_temp=q_temp; qb_temp=qb_temp; end if; end process;q=q_temp;qb=qb_temp;end rtl;. 同步D触发器 library ieee;use ieee.std_logic_1164.all;entity synd is port(clk,d:in std_logic; q,qb:out std_logic);end synd;architecture rtl of synd is signal q_temp,qb_temp:std_logic;begin process(clk) begin if(clk=1)then q_temp=d; qb_temp=not d; else q_temp=q_temp; qb_temp=qb_temp; end if; end process;q=q_temp;qb=qb_temp;end rtl; 带异步置位复位边沿（上升沿）D触发器library ieee;use ieee.std_logic_1164.all;entity adff is port(clk,d,r,s:in std_logic; q,qb:out std_logic);end adff;architecture rtl of adff is signal q_temp,qb_temp:std_logic;begin process(clk,r,s) begin if(r=0 and s=1)then q_temp=1; qb_temp=0; elsif(r=1 and s=0)then q_temp=0; qb_temp=1; el