nvidia设计验证笔试题Clock笔试

NVIDIA 2016 Campus RecruitmentExam Test Paper SH-ASIC-DVCover PageTotal pages: 10Exam Duration: 90 minutes* Please answer all the questions in EnglishApplied Position: ASIC Design/Verification Engineer（Clock）Candidate Chinese Full Name/中文名许泽昊Candidate School Name/毕业学校天津大学Candidate Contact Number/手机号andidate E-mail address/邮箱地址Current Degree/学历Master Graduation Time/毕业时间 2017 / 1 (Year/ Month)Major/专业 微电子The two questions below are used only for reference, they are not criteria for hiring. Please fill in accurately.(以下两问题仅作为参考信息，不作为新员工录用标准, 请如实填写)Availability for Internship before graduation/毕业前能否作实习生(Yes/No) 是When will be available for internship/何时可以开始实习2017 2Total Points ( 80 )Please fill Interviewee column to rate yourself on below items from 15 before you start the written test:2 - below average3 - on average4 - good5 - excellentItemsIntervieweeInterviewer AInterviewer BBasic Logic Design(combinational logic/sequential logic)excellentBasic scripting language(Perl or Python, or )goodC/C+ programminggoodProblem SolvingexcellentCommunication Skills (express clearly, explain logically)excellentNote:1. Read questions carefully and answer as much as you can.2. There are scratch papers provided, if you dont have them, please speak out.3. You can select English or Chinese to answer questionsQuestion1 (10 points): Design the schematic for the logic ofnew_en = eco_en ? eco_mask & en : en;(Please ONLY use NOR2 cells, only “eco_en”, “en” and “eco_mask” are the inputs to your logic, and try to use as less cells as possible) Question 2 (10 points): #1: What is setup timing and hold timing? You can draw diagram or waveform to explain. #2: What is clock jitter and its impact to timing?Question 3 (10 points): Draw design diagram or state machine for following sequence detection logic: if input sequence of “0110” shows up, output 1b1; otherwise, outputs 1b0. Please list how many registers your design need, can it be reduced?输出1个输入3个 可以Question 4 (10 points): Please write down Verilog code for sync & async reset DFF, and draw out schematic, list their requirements, advantage or shortage.Question 5 (20 points): set up a testbench and testing code based on Verilog or SystemVerilog, to verify a 10-bit full-adder which working on 100MHZ clock, write testplan and list all the testpoints first.Question 6 (10 points): Use Perl|Python|Tcl|Shell|C to write a script for below question, you can choose either 1 from below 2 questions, or finish both of them if youre able.#1: Read the file of “people.list”, and find out the ones who have nvidias mail-boxes (with ), and print them out into file “nvidia.list” in alphabetical order of their names.mail.list file looks like:Bob bob_Philipphilip_2006JSHR E#!/e/programfiles/perl/bin/perlopen(infile,people.list)|die(Could not open file); original=;copy=original;close(infile);open(outfile,nvidia.list); foreach $copy(copy)chomp($copy);if($copy=//) print outfile $copyn; #2: For all files under current dir, rename the files name if “tlit4” or “TLIT4”