6-2译码器chenyu.ppt

ClassexerciserealizethelogicfunctionFwith3-to-8decoderandlogicgates.,F=(X,Y,Z)(1,2,4,5),6.4decoder译码器,ReviewofLastClass,6.4.1BinaryDecoder(二进制译码器)n-to-2ndecoderThemostcommondecodercircuitisann-to-2ndecoderorbinarydecoder.Suchadecoderhasann-bitbinaryinputcodeanda1-out-of-2noutputcode.,ReviewofLastClass,Designit!,Y3=EN.I1.I0,Y2=EN.I1.I0,Y1=EN.I1.I0,Y0=EN.I1.I0,ReviewofLastClass,n-to-2ndecoder,Yi=ENmi,0XX00001000001101001011001001111000,inputsENI1I0,outputsY3Y2Y1Y0,Thetruthtablefora2-to-4binarydecoder,当输入使能端(EN)有效时Yi=mi,Dontcarenotation(无关符号),ReviewofLastClass,6.4.2LogicSymbolsforLarger-ScaleElements,Withrespecttoactivelevels,itsimportanttouseaconsistentconventiontonamingtheinternalsignalsandexternalpins.,G1,G2A-L,G2B-L,Y0-L,B,C,Y7-L,A,ReviewofLastClass,The74x138isacommerciallyavailableMSI3-to-8decoder.the74x138hasactive-lowoutputs.,(P387),ReviewofLastClass,m5,M5,ReviewofLastClass,Yi=ENmi,Yi_L=Yi=(ENmi),EN=G1G2AG2B=G1G2A_LG2B_L,m5,补充：用译码器和逻辑门实现逻辑函数,F=(X,Y,Z)(0,3,6,7)=(X,Y,Z)(1,2,4,5),对于二进制译码器：Yi=ENmi当使能端有效时，Yi=mi对低电平有效输出：Yi_L=Yi当使能端有效时，Yi_L=mi=Mi,用译码器和逻辑门实现逻辑函数,ZYX,F=(X,Y,Z)(0,3,6,7),当使能端有效时Yi=mi,对低电平有效输出：Yi_L=Yi=mi,用译码器和逻辑门实现逻辑函数,ZYX,F=(X,Y,Z)(0,3,6,7),=M1M2M4M5,=m1m2m4m5,F=(X,Y,Z)(1,2,4,5),ZYX,74x139,Truthtable?,Example3:The74x139Dual2-to-4Decoder,Whatistheequationfortheexternaloutputsignal1Y0-L?,74x139,Truthtable,Example3:The74x139Dual2-to-4Decoder,1Y0-L=1G(1B1A),74x139,Howtodesignthe4-to-16decoder?,6.4.4CascadingBinaryDecoders(级联二进制译码器）(P390),思路：16个输出需要片74x138？,任何时刻只有一片在工作。4个输入中，哪些位控制片选哪些位控制输入,Example4:designthe4-to-16decoder,Consider:Howtomakea5-to-32Decoderwith3-to-8Decoder?(思考：用74x138设计5-32译码器)(32个输出需要多少片74x138？)(控制任何时刻只有一片工作)(利用使能端),Consider:Howtomakea5-to-32Decoderwith3-to-8Decoder?(思考：用74x138设计5-32译码器)Controlinputsofthreelow-orderbitsofa5-bitcodeword(5个输入的低3位控制输入)Controlchipsoftwohigh-orderbitsofa5-bitcodeword(5个输入的高2位控制片选),Example5:designthe5-to-32decoder,74x139,(P391),补充：用译码器和逻辑门实现逻辑函数,F=(X,Y,Z)(0,3,6,7)=(X,Y,Z)(1,2,4,5),对于二进制译码器：Yi=ENmi当使能端有效时，Yi=mi对低电平有效输出：Yi_L=Yi当使能端有效时，Yi_L=mi=Mi,用译码器和逻辑门实现逻辑函数,ZYX,F=(X,Y,Z)(0,3,6,7),当使能端有效时Yi=mi,对低电平有效输出：Yi_L=Yi=mi,用译码器和逻辑门实现逻辑函数,ZYX,F=(X,Y,Z)(0,3,6,7),=M1M2M4M5,=m1m2m4m5,F=(X,Y,Z)(1,2,4,5),ZYX,BCDDecoder(二十进制译码器),Inputs:4-bitBCDcodeOutputs:1-out-of10Code,多余的6个状态如何处理？,输出均无效：拒绝“翻译”,作为任意项处理电路内部结构简单,二-十进制译码器,任意项,6.4.8Seven-SegmentDecoders(七段显示译码器)(P408),Normallyuse(常用的有)：Light-EmittingDiodes（LED,半导体数码管）Liquid-CrystalDisplay（LCD,液晶数码管）,Inputcode:4-bitBCD输入信号：BCD码（用A3A2A1A0表示）OutputCode:Seven-SegmentCode输出：七段码（的驱动信号）ag1表示亮(On)，0表示灭(Off),1111110,1101101,0011111,Seven-SegmentDecoders(七段显示译码器),七段显示译码器的真值表,DecodersinVerilog,Chapter6,Table6-20.thedecoderinFigure6-32modulevr2to4dec(I0,I1,EN,Y0,Y1,Y2,Y3);inputI0,I1,EN;outputY0,Y1,Y2,Y3;wireNOTI0,NOTI1;INVU1(NOTI0,I0);INVU2(NOTI1,I1);AND3U3(Y0,NOTI0,NOTI1,EN);AND3U4(Y1,I0,NOTI1,EN);AND3U5(Y2,NOTI0,I1,EN);AND3U6(Y3,I0,I1,EN);endmodule,case语句,case(case_expr)case_item_expr,case_item_expr:procedural_statement.default:procedural_statementendcasecase语句首先对条件表达式case_expr求值，然后依次对各分支项求值并进行比较，第一个与条件表达式值相匹配的分支中的语句被执行。可以在1个分支中定义多个分支项；这些值不需要互斥。缺省分支覆盖所有没有被分支表达式覆盖的其他分支。分支表达式和各分支项表达式不必都是常量表达式。,Table6-21.3-to-8binarydecodermodulevr74x138a(G1,G2A_L,G2B_L,A,Y_L);inputG1,G2A_L,G2B_L;input2:0A;output0:7Y_L;reg0:7Y_L;always(G1orG2A_LorG2B_LorA)beginif(G1endendmodule,6.5Encoder,ENCODER(P408),Ifthedevicesoutputcodehasfewerbitsthantheinputcode,thedeviceisusuallycalledanencoder.Probablythesimplestencodertobuildisa2n-to-norbinaryencoder.,encoder（编码器）,2ninputs,noutputs,encoder（编码器）,Y0=I1+I3+I5+I7,Y1=I2+I3+I6+I7,Y2=I4+I5+I6+I7,前提：任何时刻只有一个输入端有效。,2ninputs,noutputs,encoder（编码器）,Y0=I1+I3+I5+I7,Y1=I2+I3+I6+I7,Y2=I4+I5+I6+I7,前提：任何时刻只有一个输入端有效。,Trouble:WhenmorethanOneInputsareasserted?,优先级（priority）,Ifmultiplerequestscanbemadesimultaneously,howcantheencodingdevicedecidewhich?,Thesolutionistoassignprioritytotheinputlines,sothatwhenmultiplerequestsareasserted,theencodingdeviceproducesthenumberofthehighest-priorityrequestor.Suchadeviceiscalledapriorityencoder.(P408),6.5.1PriorityEncoders(P410)(优先编码器),将I0I7转换为H0H7，保证其中，任何时刻只有一个有效,H7=I7H6=I6I7H5=I5I6I7H0=I0I1I2I6I7A2=H4+H5+H6+H7A1=H2+H3+H6+H7A0=H1+H3+