集成电路课程设计实习内容.ppt

集成电路课程设计,7月1525日：集成电路课程设计7月2628日：撰写课程设计报告,集成电路课程设计题目,1.DESIGNFLIP-FLOP2.DESIGNACMOS8-BITALU3.DESIGNACMOS8-BITACCUMULATOR4.DESIGNACMOS8-BITMULTIPLIER5.DESIGNA8-BITBIDIRECTIONALSHIFTREGISTER6.DESIGNASYNCHRONOUS8-BITUPANDDOWNCOUNTER1必做（已做），26选作1个或自拟题目,集成电路课程设计,APseudo-RandomCodeGenerator8-bitbinarydividerCRC(cyclicredundancychecker).7x4SignedParallelDivisionCircuitAutomobileLockingControlSystemProgrammablecounter,参考电路,DFFALUFULLADDERN-BITADDERMULTIPLIER,DFF,DFF,DFF,C2MOS,DFF,TSPCRegister,ALU,FullAdder,FULLADDERSCHEMATIC,ComplimentaryStaticCMOSFullAdder,FULLADDERSCHEMATIC,TheMirrorAdder,CMOSTGFullAdderCircuit,np-CMOSAdderCircuit,N-bitAdder,TheRipple-CarryAdder,N-bitAdder,超前进位加法器（进位逻辑）,N-bitAdder,Ripple-CarryAdderLookAheadCarry-BypassAdderCarry-SelectAdder,MULTIPLIER,TheArrayMultiplier,MULTIPLIER,Carry-SaveMultiplier,HowtoGetStarted,Findrelevantreadingmaterials.DevelopasetofspecificationsthatmeettherequirementsofthechosenapplicationMakeahighlevelroughsketchDivideandconquerMakeascheduleandsticktoit,课程设计报告要求,摘要选题意义、背景，基本理论，方案选择设计详细内容ASIC设计流程代码描述及仿真向量仿真验证（VerilogXL或NC-lanch）逻辑综合布局布线版图生成DRC，EXTRACT，LVS定制设计流程电路原理及电路设计电路仿真验证（VerilogXL或NC-lanch）版图设计DRC，EXTRACT，LVS最高工作频率分析结论（功能、面积、功耗、延时）,SomeFinalTips,Startearly;dontleaveanythinguntillastminute.Periodicallysavebackups.Keeptrackofwhatneedstobeturnedinasyougoalong.,SomeDesignTips,Makeeverythingmodular,andtestoftenateverystep.Trytokeepeverythingastandardrectangularshape,includingfinaldesign.UsingEulerpathstocreateefficientlayoutsforcomplexgatesisbetterthanstringingtogethermanysimplegates.Alwayskeepinmindbigpicture.HowamIgoingtorouteinputs/powertoeachblockinthefinallayout?UsewideVddandGnd