基于dsp的lcd模块设计 tms320c55x dsp overview ——tms320c55x dsp 概述 英文翻译

毕业设计（论文）外文参考资料及译文译文论文题目TMS320C55XDSPOVERVIEWTMS320C55XDSP概述学生姓名齐蕾学号0660133311专业MO6通信工程所在学院龙蟠学院指导教师姜志鹏职称讲师2009年12月20日TMS320C55XDSPOVERVIEWFROMWWWTICOMREADTHISFIRSTABOUTTHISMANUALTHISMANUALISFORTHEPERIPHERALSTHATAREONTHEDIGITALSIGNALPROCESSORSDSPSINTHETMS320C55XC55XDSPGENERATIONTHISMANUALISINTRANSITIONMOSTPERIPHERALINFORMATIONHASBEENREVISEDANDMOVEDFROMCHAPTERSINTHISMANUALTOSEPARATEDOCUMENTSTHESESEPARATEDOCUMENTSAREREFERENCEDINCHAPTER1THEPERIPHERALINFORMATIONTHATISSTILLINTHISMANUALISBEINGREVISEDANDWILLBEINSEPARATEDOCUMENTSINTHEFUTUREWHENTHEREVISIONSARECOMPLETE,THISMANUALISTOREMAINASANOVERVIEWTHATPOINTSTOALLOFTHESEPARATEDOCUMENTSINSOMECASES,INFORMATIONHASBEENMOVEDFROMTHISMANUALTOTHEDEVICESPECIFICDATAMANUALSTMS320C55XDSPPERIPHERALSOVERVIEW1INTRODUCTIONTHEPERIPHERALSOFTHETMS320C55XC55XDSPGENERATIONANDINDICATESHOWMANYCOPIESOFEACHPERIPHERALAREONTHESPECIFICC55XDEVICESONAGIVENDEVICE,SOMEPERIPHERALSMAYSHAREPINS,MAKINGTHEPERIPHERALSUSEMUTUALLYEXCLUSIVESEETHEDEVICESPECIFICDATAMANUALFORDETAILSFORADETAILEDDESCRIPTIONOFAPERIPHERAL,SEETHECHAPTERORDOCUMENTLISTEDINTHELASTCOLUMNOFTHETABLEIFAPERIPHERALHASITSOWNREFERENCEGUIDE,THETABLESHOWSTHELITERATURENUMBERSPRUXXXFORTHATREFERENCEGUIDEIFYOUAREVIEWINGTHETABLEONLINE,YOUCANCLICKTHELITERATURENUMBERTOVIEWORDOWNLOADAPORTABLEDOCUMENTFORMATPDFFILEOTHERWISE,YOUCANFINDTHEPDFFILESONTHEINTERNETATWWWTICOMTIPENTERTHELITERATURENUMBERINTHESEARCHBOXPROVIDEDATWWWTICOMALLINFORMATIONABOUTGENERALPURPOSEI/OPINSANDSYSTEMCONTROLREGISTERSHASBEENMOVEDFROMTHISDOCUMENTTOTHEDEVICESPECIFICDATAMANUALS2ANALOGTODIGITALCONVERTERADCTHEADCISDESCRIBEDINTHETMS320VC5507/5509DSPANALOGTODIGITALCONVERTERADCREFERENCEGUIDESPRU586,ANDTHETMS320VC5505SUCCESSIVEAPPROXIMATIONSARANALOG/DIGITALCONVERTERADCUSERSGUIDESPRUFP13CLOCKGENERATORTHISCHAPTERDESCRIBESTHECLOCKGENERATORTHATISINTMS320VC5509,TMS320VC5509A,ANDTMS320VC5510DSPSTHECLOCKGENERATORFORC5505ISDESCRIBEDINTHETMS320VC5505DSPSYSTEMUSERSGUIDESPRUFP0THECLOCKGENERATORFORC5504ISDESCRIBEDINTHETMS320VC5504DSPSYSTEMUSERSGUIDESPRUGL6THECLOCKGENERATORDESCRIBEDHEREACCEPTSANINPUTCLOCKATTHECLKINPINANDENABLESYOUTOMODIFYTHATSIGNALINTERNALLYTOPRODUCEANOUTPUTCLOCKWITHTHEDESIREDFREQUENCYTHECLOCKGENERATORPASSESTHISOUTPUTCLOCKTHECPUCLOCKTOTHECPU,TOPERIPHERALS,ANDTOOTHERMODULESINSIDETHEC55XDSPTHECPUCLOCKISALSOPASSEDTHROUGHA1PROGRAMMABLECLOCKDIVIDERTOTHECLKOUTPINCHECKTHEDEVICESPECIFICDATAMANUALFORADDITIONALCLOCKGENERATIONINFORMATIONNOTEFORINFORMATIONABOUTCLOCKGENERATIONINOTHERDEVICES,SEETABLE131INTRODUCTIONTOTHEDSPCLOCKGENERATORTHEDSPCLOCKGENERATORSUPPLIESTHEDSPWITHACLOCKSIGNALTHATISBASEDONANINPUTCLOCKSIGNALCONNECTEDATTHECLKINPININCLUDEDINTHECLOCKGENERATORISADIGITALPHASELOCKLOOPPLL,WHICHCANBEENABLEDORDISABLEDYOUCANCONFIGURETHECLOCKGENERATORTOCREATEACPUCLOCKSIGNALTHATHASTHEDESIREDFREQUENCYTHECLOCKGENERATORHASACLOCKMODEREGISTER,CLKMDSEESECTION38,FORCONTROLLINGANDMONITORINGTHEACTIVITYOFTHECLOCKGENERATORFOREXAMPLE,YOUCANWRITETOTHEPLLENABLEBITINCLKMDTOTOGGLEBETWEENTHETWOMAINMODESOFOPERATIONINTHEBYPASSMODESEESECTION33,THEPLLISBYPASSED,ANDTHEFREQUENCYOFTHEOUTPUTCLOCKSIGNALISEQUALTOTHEFREQUENCYOFTHEINPUTCLOCKSIGNALDIVIDEDBY1,2,OR4BECAUSETHEPLLISDISABLED,THISMODECANBEUSEDTOSAVEPOWERINTHELOCKMODESEESECTION34,THEINPUTFREQUENCYCANBEBOTHMULTIPLIEDANDDIVIDEDTOPRODUCETHEDESIREDOUTPUTFREQUENCY,ANDTHEOUTPUTCLOCKSIGNALISPHASELOCKEDTOTHEINPUTCLOCKSIGNALTHELOCKMODEISENTEREDIFTHEPLLENABLEBITOFTHECLOCKMODEREGISTERISSETANDTHEPHASELOCKINGSEQUENCEISCOMPLETEDURINGTHEPHASELOCKINGSEQUENCE,THECLOCKGENERATORISKEPTINTHEBYPASSMODETHECLOCKGENERATORALSOHASANIDLEMODESEESECTION35FORPOWERCONSERVATIONYOUPLACETHECLOCKGENERATORINTOITSIDLEMODEBYTURNINGOFFTHECLKGENIDLEDOMAINFORINFORMATIONONTURNINGONANDOFFIDLEDOMAINS,SEESECTION8,IDLECONFIGURATIONSTHEOUTPUTOFTHECLOCKGENERATORORADIVIDEDDOWNVERSIONOFTHATOUTPUTCANBESEENONTHECLKOUTPINFORDETAILS,SEESECTION36,THECLKOUTPINANDTHEASSOCIATEDCLOCKDIVIDER32OPERATIONALFLOWOFTHEDSPCLOCKGENERATORFIGURE1DESCRIBETHEOPERATIONALSTATESAFOFTHEDSPCLOCKGENERATORTHECLOCKMODEREGISTERCLKMDISLOADEDBYSOFTWAREORBYADSPRESETIFTHEWRITETOCLKMDENABLESTHEPLL,THEPLLBEGINSITSPHASELOCKINGSEQUENCESTATEAIFTHEWRITEDISABLESTHEPLL,THECLOCKGENERATORENTERSITSBYPASSMODESTATEDSTATEDESCRIPTIONALOCKINGTHEPHASETHECLOCKGENERATORENTERSTHEBYPASSMODE,ANDTHEPLLLOCKSTHEPHASEOFTHEOUTPUTCLOCKSIGNALTOTHATOFTHEINPUTCLOCKSIGNALONCETHEPHASEISLOCKEDANDTHEOUTPUTSIGNALISATTHEFREQUENCYDEFINEDBYTHEPLLMULTBITSANDTHEPLLDIVBITSOFCLKMD,THECLOCKGENERATORENTERSITSLOCKMODESTATEBYOUCANRECONFIGURETHECLOCKGENERATORBYWRITINGTOCLKMDBLOCKMODEINTHELOCKMODE,THEPLLISGENERATINGANOUTPUTSIGNALWITHTHESELECTEDFREQUENCYTHEOUTPUTSIGNALISPHASELOCKEDTOTHEINPUTSIGNALIFTHEPLLLOSESTHELOCKANDTHEIOBBITOFCLKMDIS1,THECLOCKGENERATORRETURNSTOTHEBYPASSMODEANDREACQUIRESTHELOCKSTATEAIFTHEIOBBITIS0,THECLOCKGENERATORDOESNOTREACQUIRETHELOCKANIDLEINSTRUCTIONCANPLACETHECLOCKGENERATORINTOITSIDLEMODESTATECTOCHANGETOTHEBYPASSMODEORTORECONFIGURETHECLOCKGENERATORINOTHERWAYS,YOUCANWRITETOCLKMDCIDLEMODEENTEREDFROMTHELOCKMODEANIDLEINSTRUCTIONHASPLACEDTHECLOCKGENERATORINTOITSIDLEMODEIFTHEIDLEMODEISPROPERLYEXITED,THECLOCKGENERATORSTARTSAGAINANDREACQUIRESTHEPHASE2LOCKSTATEATHEMETHODUSEDTOREACQUIRETHELOCKDEPENDSONTHEIAIBITOFCLKMDDBYPASSMODETHEPLLISDISABLED,ANDTHECLOCKGENERATORISINTHEBYPASSMODETHEDIVIDERWITHINTHECLOCKGENERATORPRODUCESANOUTPUTCLOCKSIGNALATTHEFREQUENCYDEFINEDBYTHEBYPASSDIVBITSOFCLKMDANIDLEINSTRUCTIONCANPLACETHECLOCKGENERATORINTOITSIDLEMODESTATEETOCHANGETOTHELOCKMODEORTORECONFIGURETHECLOCKGENERATORINOTHERWAYS,YOUCANWRITETOCLKMDEIDLEMODEENTEREDFROMTHEBYPASSMODEANIDLEINSTRUCTIONHASPLACEDTHECLOCKGENERATORINTOITSIDLEMODEIFTHEIDLEMODEISPROPERLYEXITED,THECLOCKGENERATORSTARTSAGAININTHEBYPASSMODE33BYPASSMODEWHENTHEDSPCLOCKGENERATORISINTHEBYPASSMODEANDTHEPHASELOCKLOOPPLLISDISABLED,THEFREQUENCYOFTHEOUTPUTCLOCKSIGNALISEQUALTOTHEFREQUENCYOFTHEINPUTCLOCKSIGNALDIVIDEDBY1,2,OR4331ENTERINGANDEXITINGTHEBYPASSMODETOENTERTHEBYPASSMODE,WRITEA0TOTHEPLLENABLEBITINTHECLOCKMODEREGISTERCLKMDTHEPLLWILLBEDISABLEDTOEXITTHEBYPASSMODE,WRITEA1TOTHEPLLENABLEBITTHEPLLWILLSTARTUPANDENTERITSPHASELOCKINGSEQUENCEAFTERTHEPLLISGENERATINGTHECONFIGUREDOUTPUTFREQUENCYANDTHEPHASEOFTHEOUTPUTCLOCKSIGNALISLOCKEDTOTHEPHASEOFTHEINPUTCLOCKSIGNAL,THECLOCKGENERATORENTERSTHELOCKMODEUNTILTHEN,THECLOCKGENERATORSTAYSINTHEBYPASSMODEIFTHECLOCKGENERATORISINTHELOCKMODEANDTHEPLLMUSTREACQUIREITSPHASELOCKIOB1,THECLOCKGENERATORENTERSTHEBYPASSMODEUNTILTHEPHASEISLOCKEDAGAIN332CLKMDBITSUSEDINTHEBYPASSMODE3DESCRIBESTHEBITSOFTHECLOCKMODEREGISTERCLKMDTHATAREUSEDINTHEBYPASSMODETHERESERVEDBITSINCLKMDRSVDANDTESTSHOULDNOTBEUSEDINEITHERTHEBYPASSMODEORTHELOCKMODEFORADETAILEDDESCRIPTIONOFCLKMD,SEESECTION383CLKMDBITSUSEDINTHEBYPASSMODECLKMDBITFIELDROLEINTHEBYPASSMODEPLLENABLEALLOWSYOUTOSWITCHTOTHELOCKMODEBYPASSDIVDETERMINESHOWTHEINPUTCLOCKFREQUENCYISDIVIDEDIFATALLTOPRODUCETHEOUTPUTCLOCKFREQUENCYLOCKIS0INTHEBYPASSMODE333SETTINGTHEOUTPUTFREQUENCYFORTHEBYPASSMODETHEOUTPUTFREQUENCYISDETERMINEDBYTHEINPUTFREQUENCYANDTHEVALUEINTHEBYPASSDIVBITSLOADBYPASSDIVASREQUIREDTODIVIDETHEINPUTFREQUENCYBY1,2,OR434LOCKMODEINTHELOCKMODE,THEINPUTFREQUENCYCANBEBOTHMULTIPLIEDANDDIVIDEDTOPRODUCETHEDESIREDOUTPUTFREQUENCY,ANDTHEOUTPUTCLOCKSIGNALISPHASELOCKEDTOTHEINPUTCLOCKSIGNAL341ENTERINGANDEXITINGTHELOCKMODETOENTERTHELOCKMODE,WRITEA1TOTHEPLLENABLEBITINTHECLOCKMODEREGISTERCLKMDTHEPLLWILLSTARTUPANDWILLENTERITSPHASELOCKINGSEQUENCEAFTERTHEPLLISGENERATINGTHECONFIGUREDOUTPUTFREQUENCYANDTHEPHASEOFTHEOUTPUTCLOCKSIGNALISLOCKEDTOTHEPHASEOFTHEINPUTCLOCKSIGNAL,THECLOCKGENERATORENTERSTHELOCKMODEUNTILTHEN,THECLOCKGENERATORSTAYSINTHEBYPASS3MODEIFTHECLOCKGENERATORISINTHELOCKMODEANDTHEPLLMUSTREACQUIREITSPHASELOCKIOB1INCLKMD,THECLOCKGENERATORWILLENTERTHEBYPASSMODEUNTILTHEPHASEISLOCKEDAGAINTOEXITTHELOCKMODEENTERTHEBYPASSMODE,WRITEA0TOTHEPLLENABLEBITTHEPLLWILLBEDISABLED342CLKMDBITSUSEDINTHELOCKMODETABLE4DESCRIBESTHEBITSOFTHECLOCKMODEREGISTERCLKMDTHATAREUSEDINTHELOCKMODETHERESERVEDBITSRSVDANDTESTINCLKMDSHOULDNOTBEUSEDINEITHERTHELOCKMODEORTHEBYPASSMODEFORADETAILEDDESCRIPTIONOFCLKMD,SEESECTION38CLKMDBITFIELDSROLEINTHELOCKMODEPLLENABLEALLOWSYOUTOSWITCHTOTHELOCKMODEPLLMULTANDPLLDETERMINEHOWTHEINPUTCLOCKFREQUENCYISMODIFIEDIFATALLTOPRODUCETHEDIVOUTPUTCLOCKFREQUENCYIAIDETERMINESWHETHERTHEPLLRESTARTSTHEPHASELOCKINGSEQUENCEWHENTHECLOCKGENERATOREXITSITSIDLEMODEBREAKLNINDICATESWHENTHEPHASELOCKHASBEENBROKENIOBDETERMINESWHETHERTHEPLLWILLREACQUIREALOSTPHASELOCKLOCKIS1INTHELOCKMODE343SETTINGTHEOUTPUTFREQUENCYFORTHELOCKMODETHEINPUTFREQUENCYISMULTIPLIEDBYTHEPLLMULTVALUEOFCLKMDANDISDIVIDEDACCORDINGTOTHEPLLDIVVALUEOFCLKMDPLLMULTCANBEAVALUEFROM2TO31PLLDIVCANBEAVALUEFROM0DIVIDEBY1TO3DIVIDEBY4THEOUTPUTFREQUENCYCANBECALCULATEDWITHTHEFOLLOWINGEQUATION5SHOWSSOMEEXAMPLESOFUSINGPLLMULTANDPLLDIVTOSELECTANOUTPUTFREQUENCYEXAMPLESOFSELECTINGALOCKMODEFREQUENCYPLLMULTPLLDIVOUTPUTFREQUENCY310DIVIDEBY131XINPUTFREQUENCYMAXIMUMFREQUENCY101DIVIDEBY25XINPUTFREQUENCY22DIVIDEBY32/3XINPUTFREQUENCY23DIVIDEBY41/2XINPUTFREQUENCYMINIMUMFREQUENCY4TMS320C55XDSP概述摘自WWWTICOM首先阅读关于本手册本手册是为外围设备上的数字信号处理器的TMS320C55X（C55X系列）（DSP）产品所编著的。这本手册目前正在修订中。最近期的资料进行了修改，部分章节曾在本手册作为单独的文件。这些文件中引用的第1章信息，仍然在本手册体现，目前正在修订，未来将以单独章节出现，当修改完成后，本手册是为了继续作为一个概览，指出了一些单独章节。在某些情况下，信息已被写入了某些制定的用户手册。TMS320C55XDSP概述列出的TMS320C55X（C55X系列）的其他DSP系列，并说明每个有多少其他的C55X系列设备。在一个给定的设备，一些其他设备可以共享引脚，外设使用是相互排斥的，见设备特定的数据资料手册。如需外设，见本章或表的最后一栏列出的文档的详细说明。如果周边有自己的参考指南，该表显示了该文件的、的参考指南号码（SPRUXXX）。如果您正在查看表，您可以单击文学编号，可以查看或下载一个可移植文档格式（PDF）文件。或者，你可以找到在互联网上WWWTICOMPDF文件。提示输入在WWWTICOM提供的搜索框，文献数量。所有关于通用I/O引脚和寄存器信息系统控制已被可以从这份文件的设备手册的具体数据中查看到。2模拟到数字转换器（ADC）该ADC中描述TMS320VC5507/5509DSP的模拟到数字转换器（ADC）参考指南（SPRU586）和TMS320VC5505逐次逼近（SAR）模拟/数字转换器（ADC）的用户指南（SPRUFP1）。3时钟发生器本章介绍了时钟发生器，TMS320VC5509，TMS320VC5509A，TMS320VC5510DSP这些芯片。在C5505时钟发生器中描述TMS320VC5505DSP的系统用户指南（SPRUFP0）。在C5504时钟发生器中描述TMS320VC5504DSP的系统用户指南（SPRUGL6）。时钟发生器接受这里介绍的时钟输入引脚的输入时钟，使您能够修改该内部产生的信号与所需的频率输出时钟。时钟发生器通过这输出时钟（CPU时钟）的处理器，外围设备内的C55X系列的其它模块和数字信号处理器。CPU时钟也是通过一个可编程的时钟分频器的时钟输出引脚。检查设备特定的数据增加时钟代信息手册。1注意请参阅有关的其他设备的时钟生成信息31简介DSP的时钟发生器DSP的时钟发生器提供的时钟信号是对输入时钟信号的时钟输入引脚基于DSP的连接。在时钟发生器中包括数字锁相环路（PLL），它可以启用或禁用。您可以配置的时钟发生器，能够创造一个CPU时钟信号具有所需的频率。该时钟发生器时钟模式寄存器，CLKMD（见38），控制和监测时钟发生器活动。例如，您可以读出给在CLKMD锁相环使能位之间切换的两个主要的操作模式在旁路模式（见33节），PLL的作用是跳过，并输出时钟信号的频率等于输入时钟频率信号1，2，或4分。由于锁相环被禁用，这种模式可用于节省电力。在锁定模式（见34节），输入频率可以分为两种成倍增加，产生期望的输出频率，输出时钟信号的相位锁定的输入时钟信号。锁模式进入，如果该PLL的时钟模式寄存器使能位被设置，逐步锁定序列完整。（在锁相序列，时钟发生器是保存在旁路模式）。时钟发生器也有空闲模式（见第35电源保护）。你放入其空闲模式关掉CLKGEN闲置域的时钟发生器。有关打开和关闭闲置域信息，请参见第8节，空闲配置。若使用外部时钟源，只要将外部时钟信号直接加到DSP芯片的XZ/CLKIN引脚，而XL引脚悬空若使用芯片内部的振荡器，只要在芯片的X1和XZ/CLKIN引脚之间接入一个晶体，用于启动内部振荡器。在时钟发生器输出或分裂的产出下降的版本可以在时钟输出引脚中查看到有关详细信息，请参见第36节，该时钟输出引脚及相关时钟分频器。32业务流程DSP的时钟发生器描述了DSP的时钟发生器运行状态（自动对焦）。时钟模式寄存器（CLKMD）的加载软件或DSP的复位。如果写入CLKMD使锁相环，锁相环开始其锁相序列（状态A）。如果写禁用的锁相环，它的时钟发生器进入旁路模式（状态D）。2。业务表锁定的阶段。时钟发生器进入旁路模式，和PLL锁输出时钟信号的相位对输入时钟信号。一旦阶段锁定和输出信号的频率是由锁相环的MULT位，确定了DIV的锁相环的CLKMD位，它的时钟发生器进入锁定模式（B国）。你可以重新以书面CLKMD的时钟发生器。乙锁模式。在锁定模式下，锁相环产生与选定的输出信号频率。输出信号的相位锁定输入信号。如果失去了锁相环锁与CLKMDIOB颁布位，则时钟发生器返回到旁路模式并重新获取锁（状态A），如果IOB颁布位为0，时钟发生器不2重新获取锁。空闲指令可以放置到其空闲模式时钟发生器（状态C）。要更改到旁路模式或重新配置的时钟发生器其他方式，您可以写入CLKMD。荤空闲模式（从进入锁模式）。空闲指令已经把时钟发电机将其空闲模式。如果空闲模式是正确退出时，时钟发生器再次启动和重新获取锁相（状态A）。用于重新获取方法锁取决于以色列航空工业CLKMD位。旁路模式。PLL的是残疾人和时钟发生器是在旁路模式。内部时钟发生器产生的分频输出时钟信号旁路定义DIV的对CLKMD位。空闲指令可以放置24小时发电机将其空闲模式。要更改到锁定模式或重新配置钟以其他方式生成，您可以写入CLKMD。首页空闲模式（从进入旁路模式）。空闲指令已经把时钟发电机将其空闲模式。如果空闲模式是正确退出时，时钟发生器再次启动的旁路模式