EDA与VHDL程序集锦

1、四选一选择器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY WEI ISPORT(a,b,c,d:STD_LOGIC; S0,S1:STD_LOGIC; Y:STD_LOGIC);END ENTITY;ARCHITECTURE BHV OF WEI ISSIGNAL S:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN SYYYY=d;WHEN OTHERS=NULL;END CASE; END PROCESS;END BHV;条件语句：Y=a WHEN S=”00”ELSEb WHEN S=”11”ELSENULL;END

2、;END PROCESS选择语句WITH S SELECTY=A WHEN “00”，ZWHEN OTHERS;8_3编码器IF语句PORT(din:IN_STD_LOGIC_VECTOR(0-7)Output:OUT_STD_LOGIC_VECTOR(0_2);)END CRARCHITECTURE BEHAV OF CR ISBEGIN PROCESS(din)BEGINIF(din(7)=0)THEN output=”000”;ELSEIF(din（6）=0)THEN ELSE output=”111”;END IFWHEN ELSE语句Outputoutput=”000”;3_8译码器

3、ENTITY DC ISPORT(INPUT:IN STD_LOGIC_VECTOR(2_0)OUTPUT:OUT STD_LOGIC_VECTOR(7-0);)PROCESS(INPUT)NEGINOUTPUT(0)=1WHEN INPUT=”000”ELSE0;8位移位寄存器PORT(CLK,LOAD:IN STD_LOGIC;QB:OUT STD_LOGIC;DIN:IN STD_LOGIC_VECTOR(7-0);DOUT:OUT_LOGIC_VECTOR(7-0);)END SHEF;ARCHITECTURE BEHAV OF SHFF ISSIGNAL REG8:STD_LOGIC

4、_VECTOR(7-0);BEGINPROCESS(CLK,LOAD)BEGINIF CLKEVENT AND CLK=1THEN;IF LOAD=1THEN REG8=DIN;ELSE REG8(6-0)=REG8(7-1);END IF；END IF；END PROCESSQB=REG8(0);DOUT0);ELSIF CLKEVENT AND CLK=1THENIF EN=1THENIF(LOAD=0)THENQ:=DATA;ELSEIF Q0)；END IF;END IF;END IF;END IF;IF Q=”1011”THEN COUT=1;ELSE COUT=0;END IF;D

5、OUT=Q;END PROCESS;END BEHAV;可逆计数器：ADD SUB:IN STD_LOGICIF ADD SUB=1THENQ=Q+1;ELSE Q=Q-1;模可变：PROCESS(CLK,E,STEP,MODEL)IF(CLKEVENT AND CLK=1)THENIF(E=1)THENIF(Y=UNSIGNED(MODEL)Y=”0000C1=1;ELSE Y=Y+UNSIGNED(STEP);END IFELSEIF(Y=”0000”)THENY=UNSIGNED(MODEL)ZI=1ELSE Y=Y-UNSIGNED(STEP);END IF8D锁存器PORT(CLR,

6、CLK,ENA,OE:IN STD_LOGIC;D:IN STD_LOGIC_VECTOR(7-0);Q:BUFFER STD_LOGIC_VECTOR(7-0);)ENDARCHITECTURE BHV OF L8 ISSIGNALQ1:STD_LOGIC_VECTOR(7-0);BEGINU1：PROCESS(CLK,CLR,ENA)BEGINIF CLR=0THEN Q1 =”ELSEIF CLKEVENT AND CLK=1THENIF CENT=1THEN Q1 =D;END IFEND IFIF OE=1 THEN Q=Q1;ELSE Q=”ZZZZZZZZ”;END IF;END

7、 PROCESS U1END BHV三态门：PORT(ENABLE:IN STD_LOGICDATAIN:IN STD_LOGIC_VECTOR(7-0)DATAOUT:OUT STD_LOGIC_VECTOR(7-0)BEGINPROCESS(ENABLE,ADTAIN)BEGINIF ENABLE=1THEN DATAOUT=DATAIN;ELSE DATAOUT=”ZZZZZZZZ”;END IF;END PROCESSEND BHV求补码PORT(DIN:IN STD_OGIC_VECTOR(7-0)DOUT:OUT STD_LOGIC_VECTOR(7-0)PROCESS(DIN)I

8、F(DIN(7)=0)THENDOUT=DIN;ELSEDOUT=NOT DIN+1;DOUT(7)=NOT DOUT;END IFEND PROCESS分频器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALLUSE IEEE.STD_LOGIC_ARITH.ALLUSE IEEE.STD_LOGIC_UNSIGNED.ALLENTITY EHAT IS PORT(CLKIN : IN STD_LOGIC; RESET : IN STD_LOGIC; CLKOUT : OUT STDLOGIC)；END WHATARCHITECTURE BEHAVIORAL OF

9、 WHAT IS SIGNAL REG_CLK:STD_LOGIC := 0; BEGIN CLKOUT = REG_CLK; PROCESS(CLKIN,RESET) VARIABLE CNT:INTEGER RANGE 0 TO 5:=0; BEGIN IF RESET = 0 THEN CNT :=0; REG_CLK=0; ELSIF RISING_EDGE(CLKIN) THEN CNT :=CNT + 1; IF CNT =5 THEN CNT :=0; REG_CLK=NOT REG_CLK; END IF; END IF;END PROGRESS;END BEHAVIORAL3

10、-8译码器LIBRARY IEEEUSE IEEE.STD_LOGIC_1167.ALLUSE IEEE.STD_LOGIC_UNSIGNED.ALLENTITY DC3TO8 ISPort(DIN:IN STD_LOGIC_VECTOR(2-0);DOUT:OUT BIT_VECTOR（7-0）；END DC3TO8ARCHITECTURE BEHAVE OF DC3TO8 ISBEGINDOUT=”SLL CONV_INTEGER(DIN)END BEHAVEBCD加法器PORT(DIN:IN STD_LOGIC_VECTOR(3-0)DIN2：IN STD_LOGIC_VECTOR(3-

11、0)DIN3：OUT STD_LOGIC_VECTOR(7-0)SIGINAL ADDS:STD_LOGIC_VECTOR(4-0)BEGINADDS=0&din1+0&din2Process(adds)IF(ADDS=”1001)thenDOUT=ADDSELSEDOUT=ADDS+6;END IFEND PROCESSLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY s_machine IS PORT ( clk,reset : IN STD_LOGIC; state_inputs : IN STD_LOGIC_VECTOR (0 TO 1);

12、 comb_outputs : OUT INTEGER RANGE 0 TO 15 );END s_machine;ARCHITECTURE behv OF s_machine IS TYPE FSM_ST IS (s0, s1, s2, s3); SIGNAL current_state, next_state: FSM_ST;BEGIN REG: PROCESS (reset,clk) BEGIN IF reset = 1 THEN current_state = s0; ELSIF clk=1 AND clkEVENT THEN current_state comb_outputs= 5

13、; IF state_inputs = 00 THEN next_state=s0; ELSE next_state comb_outputs= 8; IF state_inputs = 00 THEN next_state=s1; ELSE next_state comb_outputs= 12; IF state_inputs = 11 THEN next_state = s0; ELSE next_state comb_outputs = 14; IF state_inputs = 11 THEN next_state = s3; ELSE next_state = s0; END IF

14、; END case; END PROCESS; END behv;8位锁存器PORT(CLK,RST:IN STD_LOGIC;DATA:IN STD_LOGIC_VECTOR(7 DOWNTO 0);MODE:IN STD_LOGICSHIFT_LEFT,SHIFT_RIGHT:IN STD_LOGIC;Q:BUFFER STD_LOGIC_VECTOR(7DOWNTO0);END SHIFETER;AR.BEGIN PROCESS(CLK RST) BEGINWAIT UNTIL (RISING_EDGE(CLK);IF(RST=1)THEN QQQQNULL;【VHDL常用的库：STD

15、 IEEE WORK VITAL】【TYPE ST1 IS ARRAY(0 TO 15)OF STD_LOGIC】【函数function（参数方式in） 进程procedure（in out inout）】【状态机设计有MOORE(输入输出无关)MEALY.MOORE(输入输出有关)】【EDA设计流程：设计输入（功能仿真）-综合-适配（时序仿真）-仿真-rtl描述】【PLD和CPLD(乘机项结构器件EEPROM【电可擦写编程器件】)FPGA(查找表结构器件SRAM)可编程逻辑器件（PLD）的编程工艺：1，基于EEPROM或flash技术2，基于SRAM查找表的编程单元3，基于反熔丝编程单元。】

16、【结构体说明：并行语句赋值-块语句-进程语句-元件例化语句-生成语句】【PLD可编程逻辑器件FPGA现场可编程门阵列IP知识产权ISP在系统编程RTL寄存器传输级HDL硬件描述语言CAD计算机辅助设计CAM制造CAT测试CAE工程DSP数字信号处理LAB逻辑阵列块SROM静态随机存储器PIA可编程连线阵LE可编程单元LUT可编程查找表JIAG联合测试行动组TDI测试数据输入TDO测试数据输出TMS测试模块选择TCK测试时钟输入TRST测试复位输入Fitter适配器】【VHDL的程序结构模型：库与程序包调用（LIBRARY.USE）实体声明（ENTITY电路端口描述end entity）结构体描述（ARCHITECTURE电路模块功能描述）配置结构（CONFIGURATION）】【常数CONSTANT变量VARIABLE信号SIGNAL属性GENERIC位置不同，赋值符号不同，赋值后的结果不同