半加器和全加器的设计

1、实验一.半加器，全加器的设计1，半加器的设计，方法一library ieee ;use ieee.std_logic_1164.all;entity h_adder1 is port(a,b :in std_logic; c,s :out std_logic);end entity h_adder1;architecture one of h_adder1 isbegin s=a xor b;cx(0),b=x(2),c=cout);end arch;运行结果：方法二：运行结果：实验二.四选一数据选择器的设计1用case语句：library ieee;use ieee.std_logic_11

2、64.all;entity mux4_1a isport(A,B,C,D :in std_logic_vector(3 downto 0); sel :in std_logic_vector(1 downto 0); q :out std_logic_vector(3 downto 0) );end mux4_1a;architecture arch of mux4_1a isbegin process(A,B,C,D,sel)begin case sel is when 00= q q q q null;end case;end process;end arch;运行结果：2，用if语句设计

3、：library ieee;use ieee.std_logic_1164.all;entity mux4_1b isport(A,B,C,D :in std_logic_vector(3 downto 0); sel :in std_logic_vector(1 downto 0); q :out std_logic_vector(3 downto 0) );end mux4_1b;architecture arch of mux4_1b isbegin process(A,B,C,D,sel)begin IF sel =00 then q=A;elsif sel = 01 then q=B

4、; elsif sel = 10 then q=C;elsif sel = 11 then q=D;end ifend process;end arch; 用with语句设计：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mux4_1c isport(A,B,C,D :in std_logic_vector(3 downto 0); sel :in std_logic_vector(1 downto 0); q :out std_logic_vector(3 downto 0) )

5、;end mux4_1c;architecture arch of mux4_1c isbeginwith sel select q=A when 00, B when 01, C when 10, D when 11, ZZwhen others;end arch;运行结果：4，用when语句设计：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mux4_1d isport(A,B,C,D :in std_logic_vector(3 downto 0); sel :in std_

6、logic_vector(1 downto 0); q :out std_logic_vector(3 downto 0) );end mux4_1d;architecture arch of mux4_1d isbegin q=A when sel=00 else B when sel=01 else C when sel=10 else D; end arch;运行结果：实验三,可逆计数器的设计library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dswq is port(clk,di

7、r : in std_logic; q : buffer std_logic_vector(3 downto 0);end;architecture arch of dswq isbegin process(clk,q,dir)begin if clkevent and clk =1 then if dir=0 then q=q+1; else q=q-1;end if;end if;end process;end arch;运行结果：异步清零，同步置数的同步8421BCD码计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity count10 isport(clk,r,s :in std_logic; data:in std_logic_vector(3 downto 0); co :out std_logic; q:buffer std_logic_vector(3 downto 0);end count10;architecture arch of count10 isbegin co=1 when(q=1001)else 0; process(clk,r) begin if(r=0)then q=0000;