数字逻辑设计及应用：Chap5 Simulation and VerilogHDL

1、Chapter 5 Design simulation and HDL,Combinational circuit analysis Schematic entry/ Text entry and their simulations,From logic circuit to truth table,Combinational logic analysis,From logic circuit to logic equation,Combinational logic analysis,From timing diagram to truth table,Combinational logic

2、 analysis,Simulation: Design analysis before production Aided with computer tools: Schematic entry / Text entry,Design simulation,Max+Plus II from Altera .com: Include : schematic entry and HDL text editor; compiler and synthesizer; waveform editor and simulator; time analyzer; programmer,EDA Tools

3、for digital design,Open the Program,Open the Graphic editor,Select logic unit and connect them,Name your I/O and name your design,Set up a project and select the device,Name and save your design; file/project/set project to current file！ Assign /device: FLEX10K/AUTO; Check and compile your design,De

4、sign check and compile,Design check and compile,If compile was not success, the error information can be found in message window, we can perfect the design according to these message; If compile success, design results can be found in .rpt file,Report for design results,Verify the design with input

5、and output,Waveform editor and Simulation,Open the waveform editor； Click the Name area, click the List to select the ports; File/End time: select the simulation time; Option/Grid size: select the time unit; Click the value for each input, set the input waveform; Save the file after all the inputs b

6、eing set,Waveform editor and Simulation,Waveform editor and Simulation,Text entry with Verilog HDL,Chapter 5 Design simulation and HDL,Verilog HDL structure,Use text entry to replace schematic entry: Large design and time delay can be easily described ; Modification can be easily done,Verilog HDL st

7、ructure,Hardware module： Name、port and structure,Module name and IO,module majority (a,b,c,f); input a,b,c; output f; structure description; endmodule,Signal :port and wire,Two kinds of signals : port : input and output; wire : any connect nets in module; The value of signals: 0 1 z x (unknown,modul

8、e majority (a,b,c,f); input a,b,c; output f; wire w1,w2,w3; structure description; endmodule,Signal :port and wire,Logic operators for bit data,y = a,y = a | b,y = a,y = a b,Logic operations,Dataflow description,module majority (a,b,c,f); input a,b,c; output f; wire w1,w2,w3; assign w1=a endmodule,m

9、odule majority (a,b,c,f); input a,b,c; output f; assign f=(a endmodule,Dataflow description,Use built_in gates for design,Gate,Structure description,module majority (a,b,c,f); input a,b,c; output f; wire w1,w2,w3; and u1(w1,a,b); and u2(w2,b,c); and u3(w3,a,c); or u4(f,w1,w2,w3); endmodule,4-bit pri

10、me-number detector when input is (1,2,3,5,7,11,13), the output is 1, otherwise the output is 0,Bus signal and its operations,Bus: A collection of two or more related signal lines,module prime (a,f); input 3:0 a; output f; wire 3:0 w; assign w0=a3 endmodule,Bus signal and its operations,Text entry,Bus signal set,Bus signal set,module bus (a,b,y1,y2,y3); input7:0 a,b; output7:0 y1,y2,y3; assign y1=a endmodule,Bus signal and its operations,B