Power IC Design.ppt

1、LAB802 低功率混合訊號晶片實驗室,IC DESIGN,Student: Shih-Wei Wang,Current Bias (Temperature Effect,1)When Vgs Vt ，由Vt決定。 (小電流時ID隨升溫而提高,2)When Vgs Vt ，由決定。(大電流時ID隨升溫而降低,T Vto,ID,ID,VBN1,VBN1,Top Diagram,3,Mixed-Signal and Power IC Lab,Start Up & Bandgap,低功率混合晶片設計實驗室 LAB 802,4,on,off,Start Up,Bandgap,ILoss,23.5u V

2、DD=5V,低功率混合晶片設計實驗室 LAB 802,5,I_OP=8u,3u,500n,1.5u,6u,1.5u,BG close-loop bode plot,低功率混合晶片設計實驗室 LAB 802,6,低功率混合晶片設計實驗室 LAB 802,6,VBG TranVDD=5V,低功率混合晶片設計實驗室 LAB 802,7,TT FF SS SF FS,Temp -40120 VDD 2.5V5V,低功率混合晶片設計實驗室 LAB 802,8,TT 4.82mV FF 5.42mV SS 5.55mV SF 4.52mV FS 14.8mV,41.7mV,1.29,1.248,ILoss

3、,低功率混合晶片設計實驗室 LAB 802,9,TT FF SS SF FS,3u,0,低功率混合晶片設計實驗室 LAB 802,clock,Advisor: Ke-Horng Chen Student: Kuan-Yu Chu,LDO,11,Loopgain(LDO,低功率混合晶片設計實驗室 LAB 802,12,DC GAIN(min):50dB,PM=60,BW:4MHz,Clock,2u,2u,1u,8u,8u,8u,4u,Loop gain(VTOI,低功率混合晶片設計實驗室 LAB 802,14,DC Gain(min):35dB,PM:80,BW:7M Hz,MOSCAP,低功率

4、混合晶片設計實驗室 LAB 802,15,FF,TT,SS,V=1V,Clock,低功率混合晶片設計實驗室 LAB 802,16,Frequency V.S VDD,I_OTA,低功率混合晶片設計實驗室 LAB 802,17,TT,FF,SS,I=2u,I=3u,I=1.5u,VDD=2.55V,低功率混合晶片設計實驗室 LAB 802,Current Sense,Advisor: Ke-Horng Chen Student:Yu-Ping Huang,Cs 10/23,Il 300m500m,Vsr,Il 300m500m,FF,TT,SS,Error =32,Error =41.8,Vsr

5、,Il 300m500m,FF,TT,SS,Error =1.06,Error =0.97,Isense,Vdd 2.5 5 0.5,24.7mV,Vsr,Temp -40 120 10,36.4mV,Vsr,Il 100m300m,Vsr,Il 100m300m,FF,TT,SS,Error =32.64,Error =38.6,Vsr,Il 100m300m,FF,TT,SS,Error =0.2,Error =1.88,Isense,Vdd 2.5 5 0.5,23.2mV,Vsr,Temp -40 120 10,22.4mV,Vsr,低功率混合晶片設計實驗室 LAB 802,Zero

6、Current Protection,Advisor: Ke-Horng Chen Student: Yi-Ping Su,Power stage (1/3,32,Path 2,Path 1,Power stage (2/3,33,Path 2,Path 1,Architecture 1by Philip K.T. Mok,34,Ibias VS. Delay,Architecture 1by Philip K.T. Mok,36,5 A,5 A,Architecture 2adding a current source,37,0 V or close to 5 V,0 A,5 V,5 A,5

7、 A,3 A,Architecture 3using only one comparator,38,3 A,3 A,Architecture 4fixed bias current,39,3 A,5 A,5 A,Bias voltage,40,Architecture 2,Architecture 1,Architecture 4,VOP,LX2,IMB2,41,Architecture 2,Architecture 1,Architecture 4,Architecture 3,VOP,LX2,IM22,42,Architecture 2,Architecture 1,Architectur

8、e 4,VOP,LX2,Delay of architecture 1 (corner,43,1.75 ns,55.5 ns,Delay of architecture 2 (corner,44,0.915 ns,69.6 ns,Delay of architecture 3 (corner,45,5.86 ns,28.4 ns,Delay of architecture 4 (corner,46,26.7 ns,197 ns,Comparison of output (speed,47,Architecture 2,Architecture 1,Architecture 4,Architecture 3,Architecture 2total current consumption,48,Architecture 1 total current consumption,49,Architecture 3total current consumption,50,Architecture 4total current consumption,51,C