(完整word版)VHDL语言实例

1、VHDL语言实例LED显示十六进制数字0例1：设计一七段显示译码器，用它来驱动七段发光管 到9和字母A到F。LED显示数码管为共阳极。LIBRARYieee;USE ieee.std_logic_1164.all;ENTITY HEX2LEDISPORT(0);0)piEX2LEDHEX :IN stdo gic_vector(3 DOWNTO肚工住 0 JLED : OUT std_logic_vector(6 TO|);图例1七段显示译码END器实体HEX2LED;ARCHITECTURE HEX2LED_arc OF HEX2LED IS BEGIN-HEX-TO-SEVEN-SEGME

2、NT DECODER-SEGMENT ENCODING-5 |1-4 |2WITH HEX SELECTLED= 1111001 when 0001,0100100 when 0010, 0110000 when 0011,0011001 when 0100,0010010 when 0101,0000010 when 0110, 1111000 when 0111,0000000 when 1000,0010000 when 1001,0001000 when 1010,0000011 when 1011,1000110 when 1100,0100001 when 1101,0000110

3、 when 1110,0001110 when 1111, 1000000 when others;END HEX2LED_arc;例 2 ：设计一个八选一数据选择器1)s 是通道选择信号 ,d0,d1,d2,d3,d4,d5,d6,d7 数据输入 out1 是数据输出dotild2d3d4d5dGd7sENTITY sels ISPORT(dO,d1,d2,d3,d4,d5,d6,d7:IN BIT;s :INTEGERRANGE0 TO 7;outl :OUT BIT);END sels;图例2 (a)gelsoutl八选一数据选择器实 体ARCHITECTURE sels_arc OF

4、sels ISBEGINWITH s SELECToutl = dO WHEN 0, di WHEN 1,d2 WHEN 2,d3 WHEN 3,d4 WHEN 4,d5 WHEN 5,d6 WHEN 6, d7 WHEN 7;数据输入Q是数END sels_arc;2)A,B,C 是通道选择信号，I0,I1,I2,I3,I4,I5,I6,I7据输出LIBRARY ieee;UliivOO- 12 34 5 6 7A B C1 II I L I I IUSE ieee.std_logic_1164.all;ENTITY mux8 ISPORT(IO,I1,I2,I3,I4,I5,I6,I7,A

5、,B,C:IN std_logic;Q :OUT stdogic);END mux8;图例2 (b)八选一数据选择器实体ARCHITECTURE mux8_arc OF mux8 ISSIGNAL sei :INTEGER ;BEGINQ = 10 AFTER 10 ns WHEN sel= 0 ELSE11 AFTER 10 ns WHEN sel= 1 ELSE12 AFTER 10 ns WHEN sel= 2 ELSE13 AFTER 10 ns WHEN sel= 3 ELSE14 AFTER 10 ns WHEN sel= 4 ELSE15 AFTER 10 ns WHEN sel

6、= 5 ELSE16 AFTER 10 ns WHEN sel= 6 ELSE17 AFTER 10 ns ;sel = 0 WHEN A= 0 AND B= 0 AND C= 0 ELSE1 WHEN A=1AND B= 0AND C=0ELSE2 WHEN A=0AND B=1AND C=0ELSE3 WHEN A=1AND B=1AND C=0ELSE4 WHEN A=0AND B= 0AND C=1ELSE5 WHEN A=1AND B= 0AND C=1ELSE6 WHEN A=0AND B= 0AND C=1ELSE7;END mux8_arc;例3:设计一 D触发器d是输入端，c

7、lk是时钟信号控制端，q是触发器的输出端。其程序如下:LIBRARY ieee;dclk图例3D触发器实体USE ieee.std_logic_1164.all;ENTITY reg ISPORT(d,clk:IN BIT; q:OUTBIT);END reg;ARCHITECTURE reg_arc OF reg IS BEGINPROCESSBEGINWAIT UNTIL clk= 1 q = d;END PROCESS;PROCESSEND reg_arc;例4:设计一基本RS触发器r、s为触发器的输入信号，q、not_q为触发器的输出信号LIBRARY ieee;USE ieee.st

8、d_logic_1164.all;图例4基本RS触发器实体ENTITY RSFF ISPORT(r,s:IN BIT;q,n ot_q:OUTBIT);END RSFF;ARCHITECTURE RSFF_arc OF RSFF ISBEGINPROCESSES)VARIABLE last_state:BIT:= O；BEGINASSERT NOT(r= 1 AND s= 1) REPORT Both r AND s equal to 1” SEVERITY error;IF r= 0 AND s= 0 THENlast_state:= last_state ;ELSIF r= 1 AND s

9、= 0 THEN last_state:= 0；ELSE - r= 0 AND s= 1 last_state:= 1；END IF;q = last_state AFTER 10 ns;not_q = NOT(last_state) AFTER 20 ns;END PROCESS;END RSFF_arc;当r和s同时等于1时，触发器处于不定状态。程序设计中设置了断言语句是为 了判断r和s都等于1时，输出终端将显示报告“ Both r ANDs equal to 1”， 同时终止模拟过程，并显示错误的严重error ,以便设计者调试和修正模块程序。从IF到ENDIF是条件语句，用到了可选项E

10、LSIF和ELSE来判别RS触发器的其 它三种情况。IF语句后面是一赋值语句，将IF语句中赋值的中间变量lsat_state 经10 ns后送到q端。图8-12是RS触发器的逻辑电路图。例5:设计一个带有异步清零、同步置数、使能控制的四位二进制计数器LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY COUNT2 ISPORT(A:IN INTEGEFRANGE0 TO 3;CLK: INSTD_LOGIC;CLR: INSTD_LOGIC;EN: INSTD_LOGIC;LD: INSTD_LOGIC;Cout: OUTINTEGER RANGE

11、0 TO 3END COUNT2;丿，图例5四位二进制计数器实体ARCHITECTURE C0UNT2_arc OF C0UNT2 IS SIGNAL SIG: INTEGER RANGE 0 TO 3;BEGINPROCESS (CLK, CLR)BEGINIF CLR = O THEN SIG = 0;ELSIF (CLKEVENT AND CLK = 1) THEN IF LD = 1 THENSIG = A;ELSEIF EN = 1 THENSIG = SIG + 1;ELSESIG = SIG;END IF;END IF;END IF;END PROCESS;Cout = SIG;

12、END COUNT2_arc例6:设计一个存储容量为28X8的RAMCS为RAM勺片选信号，WF为RAM勺写信号，RD为RAM读信号，ADR八位地址 信号，Din :八位数据输入线，Dout为八位数据输出线。library IEEE;use IEEE.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity RAM isport (WR: in STD_LOGIC;Dut图例6RAM实体RD: in STD_LOGIC;ADR: in STD_LOGIC_VECTOR (7 dow nto 0);CS: in STD_LOGIC

13、;Din: in STD_LOGIC_VECTOR (7 dow nto 0);Dout: out STD_LOGIC_VECTOR (7 dow nto 0) );end RAM;architecture RAM_arch of RAM issubtype word is std_logic_vector(7 downto 0); type memory is array (0 to 15)of word;sig nal adr_i n:i nteger range 0 to 15;sig nal sram:memory;beginadr_in=conv_integer(ADR); proc

14、ess(wr)begin if(wrevent and wr=1)then if(cs=1and wr=1)then sram(adr_in)=din after 2 ns; end if; end if; end process; process(rd,cs)begin if(rd=0and cs=1)then dout=sram(adr_in)after 3 ns;else dout next_state=yellow; red_light=0; green_light=1; yellow_light red_light=1;green_light=0;yellow_light=0;if(

15、sensor=1)thennext_state=green;elsenext_statered_light=0;green_light=0;yellow_light=1;next_state=red;end case;end process;processbeginwait until clockevent and clock=1;present_state=next_state;end process;end abc;该状态机由两个进程描述， 第一计算下一个状态逻辑， 第二个锁存下一个状态到 当前状态。例&用VHD设计一家用告警系统的控制逻辑，告警系统有来自传感器的三个 输入信号 smoke

16、、door 、water 和准备传输到告警设备的三个输出触发信号 fire_alarm 、burg_alarm 、water_alarm 以及使能信号 en 和 alarm_en 。VHDI程序描述如下：LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY alarm ISPORT(smoke,door,water:IN stdogic;en,alarm_en :IN stdogic fire_alarm,burg_alarm:OUT std_logic;water_alarm:OUT std_logic);END alarm;waier图例8家用告警

17、系统的控制逻辑电路图ARCHITECTURE alarm_arc OF alarm IS BEGINPROCESS(smoke,door,water,e n, alarm_e n) BEGINIF (smoke= 1 ) AND (en= 0)THENfire_alarm =1;ELSEfire_alarm = 0;END IF;IF (door=1 ) AND (en= 0)AND (alarm_e n=burg_alarm =1;ELSEburg_alarm = 0;END IF;IF (water=1 ) AND (en= 0)THENwater_alarm =1;ELSEwater_alarm = 0;END IF;END PROCESS;END alarm_arc;O ) TH