电子科技大学2010期末数字电子技术考试题A卷-参考答案

1、精品文档电子科技大学二零零九至二零一零学年第二 学期期 末 考试数字逻辑设计及应用课程考试题 A卷（120分钟）考试形式：闭卷考试日期2010年7月12日课程成绩构成：平时20 分， 期中 20分， 实验 0分， 期末60分-一-二二三四五六七八九十合计复核人 签名得分签名To fill your answers in the blanks (1 x25)1. If X 10= - 110, then Xtwos-complemen=10010010 2,X ones-complemen=100100012. (Assumed the number system is 8-bit long)2

2、. Performi ng the followi ng nu mber system conv ersi ons:A. 101011002=0001110100102421B. 162510=0100100101011000excess-3C. 1010011 GRAY =100110008421BCD3. If Fa,b,c(1,2,3,6), then FD a,b,c ( 1, 4, 5, 6 )= a,b,c (0, 2, 3, 7 ).4. If the parametersof 74LS-series are defined as follows: VoLmax = 0.5 V,

3、 VoHmin = 2.7 V,ViLmax = 0.8 V, ViHmin = 2.0 V, then the low-state DC noise margin is _0.3V,thehigh-state DC no ise margin is 0.7V5. Assig ning 0 to Low and 1 to High is called positive logic. A CMOS XOR gate in positive logicis called XNOR gate in negative logic.6. A sequential circuit whose output

4、 depends on the state alone is called a Mooremach ine.7. To desig n a 001010 serial seque nee gen erator by shift registers, the shift register should n eed4 一 bit as least.8. If we use the simplest state assig nment method for 130 sates, the n we n eed at least8 state variables.9. One state transit

5、ion equation is Q*=JQ+KQ. If we use D flip-flop to complete the equation.the D input terminal of D flip-flop should be have the function D=_JQ+KQ_.10. Which state in Fig. 1 is ambiguous _D11. A CMOS circuit is shown as Fig. 2, its logic function z AB +ABFig. 1gA12. If number A twos-complement =01101

6、010 and Bo nes-complement= 1001, calculateAt-B twos-complementBand indicate whether or not overflow occurs.(Assumed the number system is 8-bit long)A-B twos-complement =_01110000, overflow no13. If a RAM s capacity is 16K word8 bits, the address in puts should be14 bits; Weneed 8chips of 8K 8 bits R

7、AM to form a 16 K 32 bits ROM.14. Which is the XOR gate of the following circuit A .15. There are 2n n invalid states in an n-bit ring counter state diagram.16. An unused CMOS NOR input should be tied to logic _Low_ level or 0 .17. The fun ctio n of a DAC is tran slat ing the Digital in puts to the

8、same value of an alogoutputs.二、Complete the following truth table of taking a vote by A,B,C, when more than two of A,B,C approve a resolution, the resolution is passed; at the same time, the resolution can through if A don t agree.For A,B,C, assume 1 is indicated approval, 0 is indicated opposition.

9、 For the F,assume 1 is passed, 0 is rejecte(5)ABCF00000010010001101000101111011111、The circuit to the below realizes a comb in ati onal fun cti on F of four variables. Fill in theKarn augh map of the logic fun ctio n F realized by the multiplexer-based circuit. (674x151000111111111111000 01 11 10四、(

10、A) Minimize the logic function expressionF = A B + AC +B C+BC +B D+BD +ADE(H+G)F = A B + AC +B C+BC +B D+BD=A (B C +B C+BC +B D+BD=A +B C+BC +B D+BDD (或=A +B C+BC +B D+BD )=A +B C+BC D (或=A + BC +B+CD )(B) To find the minimum sum of product for F and useNAND-NANDgates to realize it (6)F(W,X,Y,Z) n (

11、1,3,4,6,9,11,12,14)3分F= X +XZ- 2 分=(X +XZ) = X ) (XZ)1 分五、Realize the logic function using one chip of 74LS139 and two NAND gates. (8()F(A,B,C) (2,6) G(C,D,E) (0,2,3)F(A,B,C)=C 刀(1,3)3 分 G(C,D,E)=C 刀(0,2,3)3 分Fun ction table for a 1/274x139In putsOutputsGL BAY3 L Y2 L Y1L Y0 LP 1 XX1111r 0 0011100 0

12、111010 1010110 110111六、Design a self-correcting modulo-6 counter with D flip-flops. Write out the excitation* * *equations and output equation. (QQ1Q0 denote the present states, QQ1 Qo denote the next states,Z denote the output. The state tran siti on/o utput table is as follow in gX 10 detect the i

13、n put seque nces: x=101. If x=101 is detected, the n Z=1.The in put seque nceD O NOTQ2Q1Q0Q2 Q1 Q0Z000100010011001101110111011001100100010001激励方程式:修改自启动:D2=Q0 D仁Q2D0=Q1D2=Q0 +Q2Q1D1=Q2+Q1Q0D0=Q1+Q2Q0Z=Q1 QO（2分，错-2分）（2分，错-2分） （2分，错-2分） （1分，错-1分） （1分，错-1分） （1分，错-1分） （1分，错-1分）输出方程式:Con struct a mi ni m

14、al state/output tablefor a moore sequential machine, that willoverlap one ano ther. The states are deno ted with S0S3.10For example:X:01010010101101100011Z:00010000100001000000state/output tableSXZ01S0S0S10S1S2S10S2S0S30S3S0S11S*八、Please write out the state/output table and the transition/output tab

15、le and theexcitation/output table of this state machine. (states Q2 Q1=0011, use the state name AD)xCLK(10Tran siti on/output tableState/output tableExcitati on/o utput tableQ2Q1XZ010001111010010110010101101011Q2*Q1*SXZ01ABD1BAC1CBB0DBB1S*Q2Q1XZ010001111010010110010101101011D2 D1（4分）（3分）（3分）评分标准：转移/

16、输出表正确，得4分；每错一处扣0.5分，扣完4分为止；由转移/输出表得到状态/输出表正确，得3分；每错一处扣0.5分，扣完3分为止；激励/输出表正确，得3分；每错一处扣0.5分，扣完3分为止。九、Clocked Synchronous State Machine Design( 15)74x163 is a synchronous 4-bit binary coun ter with synchronous CLEAR in put andLOAD in put. LD_L=(Q bQc), CLR_L=(Q dQb ) in the followi ng circuit.1. Finish

17、the logic circuit.2. Draw the state diagram with all states of “Q3Q2Q1Q” .( “Q3Q2Q1Q”is the output of74x163)3. Write the sequenee of Y. Y is the output of 74x151. (Assumed state of 74x163 start inQ3Q2Q1Q0=0000.)7415174163-0LDN0A0BQA1CQB1DQC1ENTQD1ENPRCO一-QCLRNCLOCKCLKinstCOUNTERQ0Q1Q2Q3-OD0D1D2D3D4D

18、5D6D7GNWNin st1 MULTIPLEXER(1) Finish the logic circuit.(见下页图)(2) Q3Q2Q1Q0:清零优先级高于置数LD_L=(Q bQc) , CLR_L=(Q d Qb )- 4 分Fun ction table for a 74x163InputsCurre nt StateNext stateOutputCLR LLD LENTENPQd Qc Qb QaQd* Qc* Q b* Q a*RCOr 0XXXX X X X0 0 0 00 :10XXX X X XD C B A0110XX X X XQd Qc QbQa011X0X X X XQd Qc QbQa01