基于FPGAverilog数字钟源码

1、module Dig_clk(input CLK_50M, input CLK_1HZ,input CLK_1K,input RSTN,input selec,input SET_add,/input SET_sub,output 23:0time_value,output 3:0LED);wire CLK_1S;wire 7:0hour,min,sec;assign LED = mode;wire 3:0mode;set_time D1(.RSTN(RSTN),.TURN(selec),.flag(mode);wire value0,value1,value2;mode_sel D2(.se

2、t_add(SET_add),.CLK(CLK_1HZ),.mode(mode2),.value(value2);wire CLK_min,CLK_h;sec_bit D3(.CLK_1S(value2),.RSTN(RSTN),.sec(sec),.CLK_min(CLK_min);mode_sel D4(.set_add(SET_add),.CLK(CLK_min),.mode(mode1),.value(value1);min_bit D5(.CLK_min(value1),.RSTN(RSTN),.min(min),.CLK_h(CLK_h);mode_sel D6(.set_add(

3、SET_add),.CLK(CLK_h),.mode(mode0),.value(value0);hour_bit D7(.CLK_h(value0),.RSTN(RSTN),.hour(hour),);assign time_value = hour*10000+min*100+sec;endmodulemodule set_time ( input RSTN, input TURN, output reg3:0flag );always(posedge TURN or negedge RSTN)beginif(RSTN)flag = 4b1000;else flag = flag2:0,f

4、lag3;endendmodulemodule mode_sel(input CLK,input set_add,input mode,output value);assign value = (mode)?set_add:CLK;endmodulemodule sec_bit(input CLK_1S,input RSTN,output reg7:0sec,output reg CLK_min);always(posedge CLK_1S or negedge RSTN)beginif(!RSTN) sec = 0;else if(sec = 8d59)begin sec = 0; CLK_

5、min = 1; endelse beginsec = sec + 1;CLK_min = 0;endendendmodulemodule min_bit(input CLK_min,input RSTN,output reg7:0min,output reg CLK_h);always(posedge CLK_min or negedge RSTN)beginif(!RSTN) min = 0;else if(min = 8d59 )beginmin = 0;CLK_h = 1;endelse beginmin = min + 1;CLK_h = 0;endendendmodulemodul

6、e hour_bit(input CLK_h,input RSTN,output reg7:0hour);always(posedge CLK_h or negedge RSTN)beginif(!RSTN) hour = 0;else if(hour =8d23) hour = 0;else hour = hour + 1;endendmodulemodule lab4_top(input CLK_50M,input RSTN,/input mode,/input 23:0num_out,output wire2:0sel_out,output wire7:0seg,output 3:0LE

7、D,input TURN,input SET_add/input SET_sub);wire CLK_1HZ;wire CLK_1KHZ;wire 23:0num_out;/wire 3:0data_num;wire 23:0time_value;wire 23:0num_value;sys_clk U1(.CLK(CLK_50M),.RSTN(RSTN),.CLK_1K(CLK_1KHZ),.CLK_1HZ(CLK_1HZ);seg_Display U2(.CLK_1K(CLK_1KHZ),.RSTN(RSTN),.num_value(time_value),.sel(sel_out),.s

8、eg(seg);wire turn, set_add;key_esk #(2)U3(.CLK_1K(CLK_1KHZ),.key_in(TURN,SET_add),.key_out(turn,set_add);Dig_clk U6(.CLK_50M(CLK_50M),.CLK_1HZ(CLK_1HZ),.CLK_1K(CLK_1KHZ),.RSTN(RSTN),.selec(turn),.SET_add(set_add),/.SET_sub(SET_sub),.time_value(time_value),.LED(LED);Endmodulemodule key_esk(input CLK_1K,input width-1:0key_in,output width-1:0key_out);parameter width = 3;reg widt