基于xilinx仿真数字电子时钟的VHDL设计课案

1、VHDL语言设计数字时钟实验性质：综合性实验级别：开课单位：信息与通信工程学院通信工程系学时：4学时一、实验目的：1学习用VHDL语言实现比较大型的电路的方法。2、继续巩固cpld技术层次化设计方法。二、实验器材：计算机、Quartus II 软件或 xilinx ISE三、实验内容：设计一数字时钟，要求具有时、分、秒、计数显示功能，以24小时循环计时；具有清零，调节小时，分钟功能；具有整点报时功能。四、实验步骤：1根据电路特点，用层次设计的概念，将此任务分成若干模块，规定每一模块的功能和各模块之间的接口。让几个学生分作和调试其中之一，然后再将各模块合起来联试。以培养学生之间的合作精神，同时加

2、深层次化设计概念。2、了解软件的元件管理深层含义，以及模块元件之间的连接概念，对于不同目录下的同一 设计，如何融合。3、模块说明：各种进制的计数及时钟控制模块（10进制、6进制、24进制）扫描分时显示，译码模块各模块都用VHDL语言编写实现电子钟原理图日“”: ZZIM_眠minuteazhuanhuanEdeled1=huanghuan?defed1= /!： 詬：|=iil D 勺!,sscDndk*41Zlwigtiu 附deled各模块程序 秒模块：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL

3、;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VCompo nen ts.all;en tity sec ond isPort ( clk : in STD_LOGIC;reset : in STD_LOGIC;semi n : in STD_LOGIC;enmin : out STD_LOGIC;daout : outST

4、D_LOGIC_VECTOR (6 dow nto 0);end sec ond;architecture Behavioral of sec ond issig nal coun t:std_logic_vector(6 dow nto 0); sig nal enmin _1,e nmin _2:std_logic; begindaout=co unt;enmin _2=(sem in and clk); enmin=(e nmin_1 or en min_2); process(clk,reset,sem in)begin if(reset=0)the n cou nt=0000000;

5、 enmin _1=0;elsif(clkevent and clk=1)then if(cou nt(3 dow nto 0)=1001thenif(cou nt16#60#)the nif(cou nt=1O11OO1)the nen min_1=1;cou nt=OOOOOOO; elsecoun t=co un t+7;end if;elsecou nt=OOOOOOO;end if;elsif(co un t16#60#)the ncoun t=co un t+1;enmin _1=0;elsecou nt=OOOOOOO;e nmin_1=0：end if;end if;end p

6、rocess;end Behavioral;分模块：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Un comme nt the followi ng library declarati on if in sta ntiati ng- any Xili nx primitives in this code.-library UNISIM;-use UNISIM.VCompo nen ts.all;en tity minu te3 is

7、Port ( clk : in STD_LOGIC;clks : in STD_LOGIC;reset : in STD_LOGIC; sethour : in STD_LOGIC; en hour : out STD_LOGIC; daout : out STD_LOGIC_VECTOR (6 dow nto 0); end minu te3;architecture Behavioral of minu te3 issig nal coun t:std_logic_vector(6 dow nto 0);sig nal en hour_1,e nhour_2:std_logic;begin

8、daout=co unt;en hour_2=(sethour and clks);en hour=(e nhour_1 or en hour_2);process(clk,reset,sethour)beginif(reset=0)the ncou nt=OOOOOOO;en hour_1=0：elsif(clkeve nt and clk=1)the nif(cou nt(3 dow nto 0)=1001thenif(cou nt16#60#)the nif(cou nt=1O11OO1)the nen hour_1=1;cou nt=OOOOOOO; elsecoun t=co un

9、t+7;en hour_1=0;end if;elsecou nt=OOOOOOO;end if;elsif(co un t16#60#)the ncoun t=co un t+1;en hour_1=0 after 100 ns;elsecou nt=OOOOOOO;e nhour_1=0：end if;end if;end process;end Behavioral;时模块：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Un c

10、omme nt the followi ng library declarati on if in sta ntiati ng- any Xili nx primitives in this code.-library UNISIM;-use UNISIM.VCompo nen ts.all;en tity hour isPort ( clk : in STD_LOGIC;reset : in STD_LOGIC; daut : out STD_LOGIC_VECTOR (5 dow nto 0); end hour;architecture Behavioral of hour issig

11、nal coun t:std_logic_vector(5 dow nto 0);begindaut=co unt;process(clk,reset)beginif(reset=O)the ncou nt=OOOOOO;elsif(clkeve nt and clk=1)the nif(cou nt(3 dow nto 0)=1001)the nif(cou nt16#23#)the ncoun t=co un t+7;elsecou nt=OOOOOO;end if;elsif(co un t16#23#)the ncoun t=co un t+1;elsecou nt=OOOOOO;en

12、d if;end if;end process;end Behavioral;转换器7library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Un comme nt the followi ng library declarati on if in sta ntiati ng - any Xili nx primitives in this code.-library UNISIM;-use UNISIM.VCompo nen ts.all;e

13、n tity s isPort ( a : in STD_LOGIC_VECTOR (6 dow nto 0);low : out STD_LOGIC_VECTOR (3 dow nto 0); high : out STD_LOGIC_VECTOR (3 dow nto 0); end s;architecture Behavioral of s isbegin low=a(3 dow nto 0);high (3) =0;high(2 dow nto 0)=a(6 dow nto 4); end Behavioral;转换器6library IEEE;use IEEE.STD_LOGIC_

14、1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Un comme nt the followi ng library declarati on if in sta ntiati ng - any Xili nx primitives in this code.-library UNISIM;-use UNISIM.VCompo nen ts.all;en tity aaa isPort ( a : in STD_LOGIC_VECTOR (5 dow nto 0);high : out STD_LO

15、GIC_VECTOR (3 dow nto 0); low : out STD_LOGIC_VECTOR (3 dow nto 0); end aaa;architecture Behavioral of aaa isbeginlow=a(3 dow nto 0);high(3 dow nto 2)=00;high(1 downto 0)=a(5 downto 4);end Behavioral;显示模块：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGN

16、ED.ALL;- Un comme nt the followi ng library declarati on if in sta ntiati ng - any Xili nx primitives in this code.-library UNISIM;-use UNISIM.VCompo nen ts.all;en tity xia nshi isPort ( num : in STD_LOGIC_VECTOR (3 dow nto 0);led : out STD_LOGIC_VECTOR (6 dow nto 0); end xia nshi;architecture Behav

17、ioral of xia nshi isbeginled=1111110whe n num=0000else0110000when num=0001else1101101whe n num=0010else1111001whe n num=0011else0110011when num=0100else1011011whe n num=0101else1011111whe n num=0110else1110000when num=0111else1111111whe n num=1000else1110011when num=1001else1110111when num=1010else0

18、011111when num=1011else1001110when num=1100else0111101when num=1101else1001111when num=1110elseOOOOOOOwhen num=1111;end Behavioral;报时模块：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VCompo nen ts.all;en tity baoshi isPort ( en hour : in STD_LOGIC;di n,daut : inSTD_LOGIC_VECTOR (6 dow nto 0);y : out STD_LOGIC);en