机器人SD卡驱动资料005STA013ApplicationNote

1、an1090application notesta013 mpeg 2.5 layer iii source decoderby ruggero de lucathis application note helps the user to work with sta013 evaluation board, installing the pc soft-ware driver, understanding how sta013 mpeg 2.5 layer iii source decoder works, and explaininghow to control the device fun

2、ctions.the document is composed by 5 main points:- mpeg 2.5 layer iii technical introduction- sta013 device description- sta013 evaluation board description- sta013 pc software driver description- general information on sta013 evaluation environmentmpeg 2.5 layer iii technical introductionan overvie

3、wsince 1988 mpeg group has been working on the standardisation of high-quality low-bitrate audio cod-ing techniques. two standards have been completed: mpeg 1 (coding of mono and stereo signals atsampling rates of 32, 44.1, and 48 khz) and mpeg 2 (backward-compatible coding of 5+1 multichannelsound

4、signals and low-bitrate coding of mono and stereo at sampling rates of 16, 22.05, 24 khz).a non standardized evolution of mpeg 2 has been developed by industry, called mpeg 2.5.it is practically the extension to the sampling rates 8, 11.025, and 12 khz, of the current mpeg 2 stand-ard.the basic idea

5、 behind perceptual coding, the general audio coding theory implemented by mpeg, is tohide the quantisation noise below the signal-dependent tresholds of hearing. in this view, the most im-portant question in perceptual coding is: how much noise can be introduced to the signal without beingaudible?.

6、the most prominent feature in psychoacoustics is masking in the frequency domain. a faintersignal is completely masked by a masker that is louder and has a similar frequency content.the overall processing chain of an mpeg encoder can summarised in the following four steps:a filter bank is used to de

7、compose the input signal into subsampled spectral components (time tofrequency domain). together with the corresponding filter bank in the decoder it forms an analysis-synthesis system.using either the time-domain input signal or the output of the analysis filter bank, an estimate of theactual (time

8、-dependent) masked threshold is computed using rules known from psychoacoustic.this is called the perceptual encoding system.the spectral components are quantized and coded with the aim of keeping the noise, which is intro-duced by quantizing, below the masking treshold. depending on the algorithm,

9、this step is done indifferent ways, from simple block companding to analysis-by-synthesis system using additionalnoiseless compression.a bitstream formatter is used to assemble the bitstream, which typically consists of the quantizedand coded spectral coefficients and some side information, such as

10、bit allocation information.march 19991/17an1090 application notethe layersrecognizing a variety of application needs, the concept of a generic coding system was envisaged. de-pending on the application, one of the three layers of the coding system with increasing complexity andperformances is chosen

11、. in all the three layers the input pcm audio signal is converted from the timeinto a time-frequency domain.this is done by a poliphase filter bank consisting of 32 subbands.in layer i and ii, a filter bank creates 32 subbands representation of the input audio stream, which arethen quantized and cod

12、ed under control of the psychoacoustic model from which a blockwise adaptivebit allocation is derived.layer i is a simplified version of the musicam coding scheme, most appropriate for consumer applica-tions, where the very low bitrate is not mandatory.layer ii introduces further compression with re

13、spect to layer i, by redundance and irrelevence removalon the scale factors, and it uses more precise quantisation.layer iii consists of a combination of the most effective modules of the aspec and musicam codingschemes. additional frequency resolution is provided by the use of a hybrid filter bank.

14、 every subband isthereby further split into higher resolution frequency lines by a mdct that operates on 18 subband sam-ples in each subband. the frame lenght is 24 ms, identical to layer ii. in layer iii, nonuniform quantisa-tion, adaptive segmentation, and entropy coding of the quantized values ar

15、e employed for better codingefficiency. the basic block diagram of a layer iii decoder is described in fig. 1.layer iii uses a short-term buffer to help the system cope with the short term difference in the bit ratedemand. only layer iii may operates in a variable rate mode, without violating the mi

16、nimum require-ments of the standard. this layer is most useful in telecommunication, in particular with narrow bandisdn, satellite links, and in all cases where the best quality at low bitrates is mandatory.figure 1: sta013 block diagraminversehuffmandecodingquantisation&descalingside informationdec

17、odingimdctinversefilterbank32 subbandsstereophonic audio signal(2*768kbit/s)encoded audio bitstream(8 kbit/s . 320 kbit/s)sta013 device descriptionancillary datathe sta013 is an mpeg 2.5 layer iii audio decoder capable of decoding elementary streams from 8up to 320 kbit/sec.the full sampling frequen

18、cies range is supported, from 8 up to 48 khz. for this reason we use the namempeg 2.5.supports all iso layer iii functionalities and worldspace extensions.programmable input data interface.programmable audio data interface.automatic output sampling rate generation.programmable oversampling clock fre

19、quency for dac.2/17 de m u l t ip l e x ing & e rro r che cksta 013an1090 application noteautomatic mpeg synchronisation, sync error detection and bistream error detection.automatic error cancelment techniques.automatic dsp speed regulation for power consumption optimisation.low power 3.0v and cmos

20、technology.10, 14.31818, 14.7456 mhz input clock.sta013 can decode layer iii compressed streams only, because the lower layers i and ii are not sup-ported by this device.it is particulary suitable for multimedia application, because it can drive the data demand by a dedicatedpin. this signal can be

21、used by the system controller to syncronize the data to sta013 input port.it can work with three different standard commercial crystals, 10.00, 14.31818, and 14,7456 mhz.the device can perform both digital volume and tone control, avoiding the use of the correspondantanalog components on the applica

22、tion.the most important dac data format (i2s, etc.) are supported. the figure 2 describes the sta013 chip partitioning.for any other technical information, refer to sta013 data sheet.figure 2. sta013 chip partitioningmpeg inputbitstreamserialinputinterfaceinputbufferdemux&error checkside infodecodin

23、ghuffmandecoderfrequencyto timetransformreconstructionfilterbankmain layer iii decoder diagrampi2cinterfaceclocksgenerationsystemserialaudiointerfaceoutputbufferdigitaltonecontroldigitalvolumecontrolspecific hardware blocksembedded ram memoriesspecific software on standard 24 bit dsp coresta013 eval

24、uation board descriptiondigital audio effectsstereophonic digital audio signal(see figure 4 electrical schematic and figure 3 functional diagram)the sta013 evaluation board (sta013evb) is useful to perform functional verification of the device op-eration. the board is connected to an external data s

25、ource by means of the input connector which provides tothe user the connection points in order to input the serial data to sta013 and to control the input dataflow speed. theinput connector is indicated on sta013evb with j6. the serial input clock line forsta013 has to be connected to pin no. 1 of j

26、6. on the sta013evb, it is connected to pin no. 6 ofsta013 (sckr). the polarity of the sta013 receiver clock can be programmed, as described in thedata sheet.the serial input data line for sta013 has to be connected pin 2 of j6. the speed of input data can becontrolled by the data_req signal of sta0

27、13 (pin no. 28) and it is connected on sta013evb to pin 4of j6. the sta013evb i2c connector (jp3) is used to interface the pc interface board to sta013. the jp3connection point no. 2 is connected to pin 4 of sta013 and is the i2c serial clock line (scl). the maxi-mum speed for this clock is 400 khz,

28、 as specified by i2c standard.3/17an1090 application notethe jp3 connection point no. 3 is connected to pin no. 3 of sta013 and is the i2c serial data line(sda). the sta013 i2c interface is used to:figure 3. sta013evb functional diagrami2cconnector jp3sta013mpeg 2.5 layer iii decoderheadphoneconnect

29、orevaluation boardsda3reset26sclso8audioamp7613j5inputconnectorj6clk/datasdisckr42856sta013so281211109oclklrclktscktsdo4321dacso885aoutlaoutrd98au944j1j2bootstrap the device by downloading the appropriate configuration file. this is done to programsta013 working with one of the three possible crista

30、l frequencies, to select the appropriate outputdata format depending on the dac used in the other application.monitor sta013 decoding operation. it is possible to read in real time all the audio program informa-tion, as sampling frequency, channels configuration, input bitstream speed, device interf

31、ace configu-ration, and ancillary data.control sta013 operation. the device implements a fully digital volume and tone control withparameters programmable via i2c interface. a microcontroller, connected to sta013 i2c interface,can change the parameters to control the volume level, the tones configur

32、ations, and the output dataformat. the sta013evb can be used by connecting the i2c port to the parallel port of a commercial pc. thei2c protocol is emulated by a dedicated pc software driver (sta013sdr) allowing the user to have onsta013 a full control. sta013sdr has a graphical user interface for a

33、n easy control of the device func-tions.the pin no. 4 of sta013evb i2c connector is connected to the pin 26 of sta013, system reset, to re-set the device even by using a sta013sdr button. the ouptut of sta013 is a digital audio signal in standard format (as described in the data sheet at pageno. 6/3

34、0). the pins no. 9, 10, 11, 12 sta013 are connected to the correspondent dac pins no. 1, 2, 3.and 4. the dac used on the sta013evb is a sigma-delta 18 bit architecture (cs4331-ks). the analog output of the converter is sent to the active speakers connectors j1 (rca-outl) and j2(rca-outr). the amplif

35、ied analog outputs are even sent to the j5 headphone connector. the am-plification is produced by means of an audio amplifier (tda 2822). on sta013evb all the mpeg decoder input and ouput digital signals can be monitored by the followingtest points:4/17figure 4. sta013evb electrical schematicamp6 2

36、ways2.7v/3.3v12j4sclresetr9 4702468101214an1090 application notec1347fc140.1fl1ferrited2greengnd135791113sdavddjp3ampvddc12vdd1resetvddr6 8.2kc104.7fc9sw1r7r80.1fgnd26tp10nfsmdavccvddall grounds4.7k4.7k2gndj6extconnected at only onepoint beneath the boardu1eu1ftptpsdascl342725scanenfilt4321101174lvx

37、04d1redr24121374lvx04tpout_clk/data_reqvddvddc112814192322vddgndc80.1fvddc6470pfc74.7nfr41k1u1a23303u1b40.1fgndsdi135sta01318pgndpvddc41nfc50.1fr13 4.7r14 4.7r264.7k74lvx0474lvx0474lvx0474lvx04tpsckr6u21721xtir1r3r2vddj3smbr274.7k5u1c6c300.1fvdd9u1d8vddvddtpvddbit-entesten7242016xtovddvddr5 1mx1 xta

38、l0100100r2210kjp1r2310kjp2src_intsdo8910111215gndc10.1fc247pfavccc347pfscktlrclktoclktptpmclklrckc150.1f4c1610fva+78r1056kc17 10faoutlr11 2.7kc29680pfoutltptpdem/sclk32cs4331-ks65agndc18 10fj1 rcaj2 rcac24 100fout118in1-sdata1u3aoutrr2156kr12 2.7kc19680pfoutrc20 0.1fr15 4.7avccc23 10fc22 100fvcc2tda

39、2822d7in1+in2+c25 100fr171kr19 56kc27 0.33fj5phonejack stereoc21 0.1fr16 4.7out2gnd34u465in2-c26 100fr181kr20 56kc28 0.33fd98au935atest point name(tp)resetsdascli2c datai2c datai2c clockdescriptionreference pin of u2pin 26pin 3pin 4data_reqsdisckrsdo1scktlrclkoclk(see figure 4 for details)data reque

40、st line inputserial data inputserial clock inputserial data outputserial clock outputleft/right clock outputdac oversampling clock outputpin 28pin 5pin 6pin 9pin 10pin 11pin 125/17an1090 application notesta013 master clockthe sta013 can use three different master clock frequencies, each one obtained

41、 by an external crystaloscillator x1. the user can even evaluate these three different input frequencies by connecting a func-tion generator to j3-smb connector.on sta013evb the mounted crystal is a standard smd sxa packaged commercial one.sta013evb signal levelsthe sta013 and all the components on

42、the board work at 3v of power supply. the sta013 evb inputconnector is bufferized by an interface ic stage (u1a - u1f are six inverters included an 74lvx04 ic) byallowing the user to use directly a data source with signals level up to 5v without further stages.power supplysta013evb has to be supplie

43、d by the j4 connector. this board uses a particular layout technique tominimizing digital and analog noise, including grounding and power supply decoupling. the allowedsupply voltage range is 2.7v - 3.3v.figure 5. sta013evb component side silkscreen (not in scale)to pc interface boardvcc = 3v- +lact

44、ivespeakersrmp3sourceheadphones6/17figure 6. 1134-137.7 pc interface board (not in scale)an1090 application note7/17an1090 application notefigure 7. pc interface schematic.8/17sta013 pc control softwarean1090 application notethe sta013evb is provided with a pc control software driver (sta013sdr), al

45、lowing the user evalu-ating all the device functions and controlling the device operation. the sta013sdr is a win3.x / win 95software that can be installed directly by the user on a standard pc. (see installation procedure section)sta013sdr panelthe graphical user interface of sta013sdr is composed

46、by:volume control barstone control barstone atten barread buttonwrite buttoncalled dal, dar, dbl, and dbr. the function implemented is thesame than the corresponding volume control i2c registers.called bass gain, bass freq, treble gain, and treble freq.thefunctions implemented are equivalent to the

47、corresponding tonecontrol i2c registers.it has equivalent function than the tone_atten i2c register.it is used to read the current i2c registers status, corresponding to thepanel functions. by pressing this button the panel will show the statusof all the displayed registers.it is used to write the c

48、urrent i2c registers status, corresponding to thepanel functions. by pressing this button the software will update thestatus of all the displayed registers.9/17an1090 application noteregisters buttonstatus buttonrun button.firmware buttonhw reset.10/17this function allow the read and/or the write op

49、-eration on all the sta013 registers. to write theregisters the user has to update the register set-ting before pressing the write button.by pressing this button the user open a windowdisplaying the status of sta013. the possiblestatus are described in the status register de-scription.in the lower part of the status window thempeg frame counter value is displayed.the function implemented by this button isequivalent to the run i2c register.by pressing this button the user opens a windowto download the sta013 patch file (if needed).this action is suggested to be preceeded by anhw reset