COA课件15讲稿.

1、William Stallings Computer Organization and Architecture 6th Edition Chapter 16 Control Unit Operation 控制器的操作控制器的操作 16.1 Micro-Operations 微操作微操作 A computer executes a program Fetch/execute cycle Each cycle has a number of steps see chapter 12 pipelining Called micro-operations OPs information flow E

2、ach step does very little Atomic(基本的或原子的基本的或原子的) operation of CPU Page 577 Constituent Elements of Program ExecutionPage 577 4 Registers Four registers are essential to instruction execution： Memory Address Register (MAR) Connected to address bus Specifies address for read or write op Memory Buffer

3、Register (MBR) Connected to data bus Holds data to write or last data read Program Counter (PC) Holds address of next instruction to be fetched Instruction Register (IR) Holds last instruction fetched Page 578 Fetch Sequence (symbolic) t1: (PC) - MAR t2: (MAR) - Memory by address bus read - Memory b

4、y control bus t3: Memory - MBR by data bus t4: (MBR) - IR (PC) +1 - PC (Maybe happen in t2,t3 and t4) AB CB DB Rules for Clock Cycle Grouping Proper sequence must be followed MAR - (PC) must precede MBR - Memory Conflicts must be avoided Must not read (R1)+(X) -R1 add the contents of location X to R

5、egister 1 , result in R1 Page 581 Execute Cycle (ADD) ADD R1,X; (R1)+(X) - R1 t1: Ad(MBR) - MAR t2: (MAR) - Memory read -Memory t3: Memory- MBR t4: (R1) + (MBR) -R1 Note no overlap of micro-operations Execute Cycle (ISZ) ISZ X increment and skip if zero if (X)+1)=0, Skip(小跳小跳 ) t1: Ad(MBR)-MAR t2: (

6、MAR)-Memory read-Memory t3:Memory-MBR t4:(MBR) + 1 - MBR t5: if (MBR) = 0 then (PC) +1 - PC (MBR) -Memory 回存回存 (MAR) -Memory write -Memory Execute Cycle (BSA) BSA X - Branch and save address Address of instruction following BSA is saved in X Execution continues from X+1 Page 582 BSA X BSA X - Branch

7、 and save address Address of instruction following BSA is saved in X Execution continues from X+1 Memory n X n+1 X+1 Procedure X BSA X Ad(return) 返回地址返回地址 Execute Cycle (BSA) BSA X ; t1: Ad(MBR) -MAR - X t2: (PC) -MBR t3: (MAR)- Memory -保护返回地址到保护返回地址到 X 地址中地址中 (MBR) -Memory write -Memory t4: (MAR)+1

8、 -PC - X+1 Problems Add R, X; (X)+(R)-R direct addressing Add A,(X); (X)+(R)-R indirect addressing CALL X; call X function, save return address on the top of stack Return; from top of stack return to PC Topic Write down all Micro operations about the following instructions (1) ADD X,R ; (2) RETURN;

9、(the return address is in the stack) Pentium Interrupt Processing (see page 447) Interrupt vector table(IVT) 中断向量表中断向量表 (chapter 12) Identifying Interrupting Module :Daisy Chain or Hardware poll菊花链菊花链(硬件轮询硬件轮询, 向量向量) (chapter 7) Interrupt Acknowledge sent down a chain Module responsible places vecto

10、r on bus CPU uses vector to identify handler routine The addresses of All ISRs Each interrupt type assigned a number Index into interrupt vector table 256 32-bit interrupt vectors Interrupts：Nonmaskable (NMI) 不可屏蔽中断不可屏蔽中断 Maskable (INTR) 可屏蔽中断可屏蔽中断 Interrupt Cycle (see page 448) Must do (simplified ): 1.Acknowledgement to interrupt request device to get device number 2.Save (PSW ”+”“或” ) C5=PQT2+ PQT2 + PQT2 (LDA+ADD+AND+) + PQ PQ -Fetch cycle PQ -Indirect