HV Process and Device高压工艺与器件

1、HV Process and Device TD-HV Agenda High voltage product application HV Technology introduction HV voltage standard device 0.5um 5V/40V Mixed-signal Technology Features 0.5um 5V/40V Mixed-signal Design Flexibility 0.5um HV Mixed-Signal Process Flow Low dissipation output CDMOS technology is created b

2、y merging LDMOS technology and CMOS technology. The majority of CDMOS processes are used for driver and power ICs. Adding BJT options, CDMOS will become BCD process. CMOS High density digital and analog CDMOS High density digital and analog; High Current output; Low dissipation output High voltage S

3、tandard Device HNW N+N+ Psub Source POLY FOX HPW HNW N+ OD CO 40V Metal l Above 30v (LDMOS-lateral double diffusion MOS) 40/25V (Vds/Vgs) device structure Critical dimension: A: Channel length A affect the breakdown of punch through and Rdson B: Drift extension TO B, BV , Major C: TO to TO space C,

4、BV, Major D: M1 overlap drain side TO D,BV, Minor E: Poly overlap FOX E, BV, Minor 1.Drain well to guard ring Provide the field isolation and reduce the latch up Drain HNW N+N+ Psub Source Gate FOX HPW A B C D E 0.5um 5V/40V Mixed-signal Technology Features Triple well LOCOS on P-sub./ 21 mask&25 la

5、yers except all options 0.5um DPTM 5V base+5V Analog+HV 40V/25V(Vds/Vgs) LDD and field punch through stop implant for N/PMOSFET Up to 3 metal layers/ Thick top metal optional Triple well architecture to isolate negative bias BPTEOS for ILD/PETEOS for IMD Polycide Poly1 for MOS gate/ Plain poly 2 for

6、 PIP/High Res. W plug for contact &vias PECVD Oxide / Nitride for passivation Plug implant for contact 0.5um 5V/40V Mixed-signal Design Flexibility 10 fundamental transistors and 4 additional options 2 PIP capacitors for low and high voltage application 5 high resistance poly resistors for different

7、 application Various parasitic BJT Thick metal for low Rdson design Triple well architecture, allow arbitrary bias on N channel device Electrical poly fuse for trimming circuit design Provide 5V STD cell library for logic design Physical verification run set and PDK on Cadence environment 0.5um HV M

8、ixed-Signal Process Flow&Modules If only normal/HVN Dep. NMOS Low Vt PMOS Dep. PMOS Thin GOX Thick GOX Dep. PMOS Vt Imp. Dep. NMOS Vt Imp. HVPMOS Vt Imp. Low Vt PMOS Imp. Normal Vt Imp. HVNF Imp. PMOS-Field Base NMOS-Field/APT Sac OX Field OX/Drive Active N/P-well HV N/P-well Deep N-well 0.5um HV Mi

9、xed-Signal Process Flow&Modules PCM Pad Al3 Via2 Al2 Via1 Al1 P+ Plug Contact Low TC Poly2 Res. ONO High Res. Low TC Res. Poly2 N/PSD Spacer N/PLDD Poly1 High Poly Res. PIP CAP(ONO) is critical layer Issue in development lHV NMOS Sub-threshold leakage HV asymmetric NMOS baseline condition 1.0E-11 1.

10、0E-10 1.0E-09 1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 00.511.522.53Vg Id Sub-threshold leak in HV NMOS VT curve compared to 5v normal NMOS device. And from the graph, this device must has a parasitical NMOS parallel to HV NMOS, the parasitical NMOS VT is higher or smaller than HV NMOS. Issue in deve

11、lopment A A B B C C Drain Source Gate A: Normal HV NMOS device B&C: Parasitical device. Test condition: Vd=0.1v, Vsub=Vs=0v, Vg sweep from 0v to 5v ABC Issue in development l5v P-field MOS leakage: A A B B Appendix Thick metal option for low Rdson Poly Fuse MOS Capacitors HV diode/Zener diode Low TC Poly resistor Hi Poly resistance HV PIP capacitors PIP capacitors HV Parasitic BJT 5V Parasitic BJT 18/25v(Vds/Vgs) HVMOS Tran. Isolated HVNMOS Tran. 40/25V (Vds/Vgs) HV