基于EDA的交通灯控制器课程设计

1、真诚为您提供优质参考资料，若有不当之处，请指正。本科课程设计报告课程名称： EDA计数与FPGA应用设计 设计题目： 交通灯控制器 实验地点： 跨越机房 专业班级： 电信0901 学号： 2009001249 学生姓名： 赵岩 指导教师： 张文爱 年 月 日 设计一：三位十进制计数显示器一、 设计目的：1、 掌握时序电路中多进程的VHDL的描述方法。2、 掌握层次化设计方法。3、熟悉EDA的仿真分析和硬件测试技术。二、设计原理三位十进制计数显示器分三部分完成，先设计十进制计数电路，再设计显示译码电路，最后设计一个顶层文件将两者连接起来。三源程序1、 三位十进制计数器的三位分三个进程描述，含有同

2、步清0信号RESET和计数使能控制信号CINLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COU3 IS PORT(CLK,RESET,CIN:IN STD_LOGIC; CO:OUT STD_LOGIC; A,B,C:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END COU3 ;ARCHITECTURE ART OF COU3 IS SIGNAL AP,BP,CP:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN KK1:PROCE

3、SS(CLK) BEGIN IF (CLKEVENT AND CLK=1) THEN IF (RESET=0) THEN AP=0000; ELSIF (CIN=1) THEN IF (AP=1001) THEN AP=0000 ; ELSE AP=AP+1; END IF; END IF; END IF; END PROCESS KK1;KK2:PROCESS(CLK) BEGIN IF (CLKEVENT AND CLK=1) THEN IF (RESET=0) THEN BP=0000; ELSIF (CIN=1) AND (AP=1001) THEN IF BP=1001 THEN B

4、P=0000; ELSE BP=BP+1; END IF; END IF; END IF; END PROCESS KK2;KK3: PROCESS(CLK) BEGIN IF (CLKEVENT AND CLK=1) THEN IF (RESET=0) THEN CP=0000; ELSIF (CIN=1) AND (AP=1001) AND (BP=1001) THEN IF CP=1001 THEN CP=0000; ELSE CP=CP+1; END IF; END IF; END IF; END PROCESS KK3;PROCESS(CLK) IS BEGIN IF CLKEVEN

5、T AND CLK=1 THEN IF AP=1001 AND BP=1001 AND CP=1001 THEN CO=1; ELSE CO=0; END IF; END IF; END PROCESS; A=AP; B=BP; CYIMAYIMAYIMAYIMAYIMAYIMAYIMAYIMAYIMAYIMAYIMAMR=0;MY0=0;MG0=1;BR=1;BY0=0;BG0=0; IF(SB AND SM)=1 THEN IF S=45 THEN STATE=B;CLR:=0;EN:=0; ELSE STATE=A;CLR:=1;EN:=1; END IF; ELSIF(SB AND(N

6、OT SM)=1THEN STATE=B;CLR:=0;EN:=0; ELSE STATEMR=0;MY0=1;MG0=0;BR=1;BY0=0;BG0=0; IF S=5 THEN STATE=C;CLR:=0;EN:=0; ELSE STATEMR=1;MY0=0;MG0=0;BR=0;BY0=0;BG0=1; IF(SM AND SB)=1THEN IF S=25 THEN STATE=D;CLR:=0;EN:=0; ELSE STATE=C;CLR:=1;EN:=1; END IF; ELSIF SB=0 THEN STATE=D;CLR:=0;EN:=0; ELSE STATEMR=

7、1;MY0=0;MG0=0;BR=0;BY0=1;BG0=0; IF S=5 THEN STATE=A;CLR:=0;EN:=0; ELSE STATE=D;CLR:=1;EN:=1; END IF; END CASE; END IF;END PROCESS CNT;END ARCHITECTURE ART;设计仿真的截图：XSKZ模块的实现简单设计思路：根据EN45、EN25、EN05M、EN05B的信号以及3个倒计时计数器的计数状态决定输出3个倒计时计数器中某个的状态输出。原理图模块：设计源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IE

8、EE.STD_LOGIC_UNSIGNED.ALL;ENTITY CSKZ IS PORT(INA:IN STD_LOGIC; OUTA:OUT STD_LOGIC);END ENTITY CSKZ;ARCHITECTURE ART OF CSKZ IS BEGIN PROCESS(INA)IS BEGIN IF INA=1THEN OUTA=1; ELSE OUTA=0; END IF; END PROCESS;END ARCHITECTURE ART;设计仿真的截图：CNT45S模块的实现简单思路：CLK上升沿到来时，若到计时使能信号和SB信号有效，CNT45S开始计数，并将输入状态通过D

9、OUT45M、DOUT45B分别输出到主、支干道显示。 设计的原理图模块： 设计源程序：3LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT45S IS PORT(SB,CLK,EN45:IN STD_LOGIC; DOUT45M,DOUT45B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END CNT45S;ARCHITECTURE ART OF CNT45S IS SIGNAL CNT6B:STD_LOGIC_VECTOR(5 DOWNTO 0); B

10、EGIN PROCESS(SB,CLK,EN45) IS BEGIN IF SB=0 THEN CNT6B=CNT6B-CNT6B-1; ELSIF(CLKEVENT AND CLK=1)THEN IF EN45=1THEN CNT6B=CNT6B+1; ELSIF EN45=0THEN CNT6BDOUT45M=01000101;DOUT45BDOUT45M=01000100;DOUT45BDOUT45M=01000011;DOUT45BDOUT45M=01000010;DOUT45BDOUT45M=01000001;DOUT45BDOUT45M=01000000;DOUT45BDOUT45

11、M=00111001;DOUT45BDOUT45M=00111000;DOUT45BDOUT45M=00110111;DOUT45BDOUT45M=00110110;DOUT45BDOUT45M=00110101;DOUT45BDOUT45M=00110100;DOUT45BDOUT45M=00110011;DOUT45BDOUT45M=00110010;DOUT45BDOUT45M=00110001;DOUT45BDOUT45M=00110000;DOUT45BDOUT45M=00101001;DOUT45BDOUT45M=00101000;DOUT45BDOUT45M=00100111;D

12、OUT45BDOUT45M=00100110;DOUT45BDOUT45M=00100101;DOUT45BDOUT45M=00100100;DOUT45BDOUT45M=00100011;DOUT45BDOUT45M=00100010;DOUT45BDOUT45M=00100001;DOUT45BDOUT45M=00100000;DOUT45BDOUT45M=00011001;DOUT45BDOUT45M=00011000;DOUT45BDOUT45M=00010111;DOUT45BDOUT45M=00010110;DOUT45BDOUT45M=00010101;DOUT45BDOUT45

13、M=00010100;DOUT45BDOUT45M=00010011;DOUT45BDOUT45M=00010010;DOUT45BDOUT45M=00010001;DOUT45BDOUT45M=00010000;DOUT45BDOUT45M=00001001;DOUT45BDOUT45M=00001000;DOUT45BDOUT45M=00000111;DOUT45BDOUT45M=00000110;DOUT45BDOUT45M=00000101;DOUT45BDOUT45M=00000100;DOUT45BDOUT45M=00000011;DOUT45BDOUT45M=00000010;D

14、OUT45BDOUT45M=00000001;DOUT45BDOUT45M=00000000;DOUT45B=00000000;END CASE;END PROCESS;END;设计仿真的截图：CNT25S模块的实现简单思路：CLK上升沿到来时，若到计时使能信号、SM信号和SB信号有效，CNT25S开始计数，并将输入状态通过DOUT25M、DOUT25B分别输出到主、支干道显示。设计的原理图模块：设计源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSI GNED.ALL;ENTITY CNT25S IS POR

15、T(SB,SM,CLK,EN25:IN STD_LOGIC; DOUT25M,DOUT25B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY CNT25S;ARCHITECTURE ART OF CNT25S IS SIGNAL CNT5B:STD_LOGIC_VECTOR(4 DOWNTO 0); BEGINPROCESS(SB,SM,CLK,EN25)ISBEGIN IF SB=0THEN CNT5B=CNT5B-CNT5B-1; ELSIF SM=0THEN CNT5B=CNT5B-CNT5B-1; ELSIF(CLKEVENT AND CLK=1

16、)THEN IF EN25=1THEN CNT5B=CNT5B+1; ELSIF EN25=0THEN CNT5BDOUNT25B=00100101;DOUT25MDOUNT25B=00100100;DOUT25MDOUNT25B=00100011;DOUT25MDOUNT25B=00100010;DOUT25MDOUNT25B=00100001;DOUT25MDOUNT25B=00100000;DOUT25MDOUNT25B=00011001;DOUT25MDOUNT25B=00011000;DOUT25MDOUNT25B=00010111;DOUT25MDOUNT25B=00010110;

17、DOUT25MDOUNT25B=00010101;DOUT25MDOUNT25B=00010100;DOUT25MDOUNT25B=00010011;DOUT25MDOUNT25B=00010010;DOUT25MDOUNT25B=00010001;DOUT25MDOUNT25B=00010000;DOUT25MDOUNT25B=00001001;DOUT25MDOUNT25B=00001000;DOUT25MDOUNT25B=00000111;DOUT25MDOUNT25B=00000110;DOUT25MDOUNT25B=00000101;DOUT25MDOUNT25B=00000100;

18、DOUT25MDOUNT25B=00000011;DOUT25MDOUNT25B=00000010;DOUT25MDOUNT25B=00000001;DOUT25MDOUNT25B=00000000;DOUT25M=00000000;END CASE;END PROCESS;END;设计仿真的截图：CNT05S模块的实现简单思路：CLK上升沿到来时，若到计时使能信号有效，CNT25S开始计数，并将输入状态通过DOUT05输出到主、支干道显示。设计的原理图模块：设计源程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNS

19、IGNED.ALL;ENTITY CNT05S ISPORT(CLK,EN05M,EN05B:IN STD_LOGIC; DOUT5:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END CNT05S;ARCHITECTURE ART OF CNT05S IS SIGNAL CNT3B:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN PROCESS(CLK,EN05M,EN05B)IS BEGIN IF(CLKEVENT AND CLK=1)THEN IF EN05M=1THEN CNT3B=CNT3B+1; ELSIF EN05B=1THEN CN

20、T3B=CNT3B+1; ELSIF EN05B=0THEN CNT3BDOUT5DOUT5DOUT5DOUT5DOUT5DOUT5YIMAYIMAYIMAYIMAYIMAYIMAYIMAYIMAYIMAYIMAYIMAYIMAYIMAYIMAYIMAYIMANULL; END CASE; END PROCESS; END ART;整体组装和测试自动转换出来的源程序：LIBRARY ieee;USE ieee.std_logic_1164.all; LIBRARY work;ENTITY Block1 IS port( CLK : IN STD_LOGIC;SM : IN STD_LOGIC;

21、SB : IN STD_LOGIC;MR : OUT STD_LOGIC;MY : OUT STD_LOGIC;MG : OUT STD_LOGIC;BR : OUT STD_LOGIC;BY : OUT STD_LOGIC;BG : OUT STD_LOGIC;DOUT1 : OUT STD_LOGIC_VECTOR(7 downto 0);DOUT2 : OUT STD_LOGIC_VECTOR(7 downto 0);END Block1;ARCHITECTURE bdf_type OF Block1 IS component cnt05sPORT(CLK : IN STD_LOGIC;

22、 EN05M : IN STD_LOGIC; EN05B : IN STD_LOGIC; DOUT5 : OUT STD_LOGIC_VECTOR(7 downto 0);end component;component cnt25sPORT(SB : IN STD_LOGIC; SM : IN STD_LOGIC; CLK : IN STD_LOGIC; EN25 : IN STD_LOGIC; DOUT25B : OUT STD_LOGIC_VECTOR(7 downto 0); DOUT25M : OUT STD_LOGIC_VECTOR(7 downto 0);end component

23、;component cnt45sPORT(SB : IN STD_LOGIC; CLK : IN STD_LOGIC; EN45 : IN STD_LOGIC; DOUT45B : OUT STD_LOGIC_VECTOR(7 downto 0); DOUT45M : OUT STD_LOGIC_VECTOR(7 downto 0);end component;component jtdkzPORT(CLK : IN STD_LOGIC; SM : IN STD_LOGIC; SB : IN STD_LOGIC; MR : OUT STD_LOGIC; MY0 : OUT STD_LOGIC

24、; MG0 : OUT STD_LOGIC; BR : OUT STD_LOGIC; BY0 : OUT STD_LOGIC; BG0 : OUT STD_LOGIC);end component;component xskzPORT(EN45 : IN STD_LOGIC; EN25 : IN STD_LOGIC; EN05M : IN STD_LOGIC; EN05B : IN STD_LOGIC; AIN05 : IN STD_LOGIC_VECTOR(7 downto 0); AIN25B : IN STD_LOGIC_VECTOR(7 downto 0); AIN25M : IN S

25、TD_LOGIC_VECTOR(7 downto 0); AIN45B : IN STD_LOGIC_VECTOR(7 downto 0); AIN45M : IN STD_LOGIC_VECTOR(7 downto 0); DOUTB : OUT STD_LOGIC_VECTOR(7 downto 0); DOUTM : OUT STD_LOGIC_VECTOR(7 downto 0);end component;signalSYNTHESIZED_WIRE_13 : STD_LOGIC;signalSYNTHESIZED_WIRE_14 : STD_LOGIC;signalSYNTHESI

26、ZED_WIRE_15 : STD_LOGIC;signalSYNTHESIZED_WIRE_16 : STD_LOGIC;signalSYNTHESIZED_WIRE_8 : STD_LOGIC_VECTOR(7 downto 0);signalSYNTHESIZED_WIRE_9 : STD_LOGIC_VECTOR(7 downto 0);signalSYNTHESIZED_WIRE_10 : STD_LOGIC_VECTOR(7 downto 0);signalSYNTHESIZED_WIRE_11 : STD_LOGIC_VECTOR(7 downto 0);signalSYNTHE

27、SIZED_WIRE_12 : STD_LOGIC_VECTOR(7 downto 0);BEGIN MY = SYNTHESIZED_WIRE_13;MG = SYNTHESIZED_WIRE_16;BY = SYNTHESIZED_WIRE_14;BG CLK, EN05M = SYNTHESIZED_WIRE_13, EN05B = SYNTHESIZED_WIRE_14, DOUT5 = SYNTHESIZED_WIRE_8);b2v_inst1 : cnt25sPORT MAP(SB = SB, SM = SM, CLK = CLK, EN25 = SYNTHESIZED_WIRE_15, DOUT25B = SYNTHESIZED_WIRE_9, DOUT25M = SYNTHESIZED_WIRE_10);b2v_inst2 : cnt45sPORT MAP(SB = SB, CLK = CLK, EN45 = SYNTHESIZED_WIRE_16, DOUT45B = SYNTHESIZED_WIRE_11, DOUT45M = SYNTHESIZED_WIRE_12);b2v_inst3 : jtdkzPORT MAP(CLK = CLK, SM = SM, SB = SB, MR = MR, MY0 = S