vhdl语言例程集锦(doc81)..doc

1、vhdl 语言例程集锦Examples of VHDL DescriptionsAdvanced Electronic Design AutomationExamples of VHDL DescriptionsAuthor: Ian Elliott of Northumbria UniversityThis a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardwa

2、re. The examples range from simple combinational logic, described interms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any IEEE compliant VHDL simulator and many can besynthesised usin

3、g current synthesis tools.Use the hierarchical links below to navigate your way through the examples:l Combinational Logicl Countersl Shift Registersl Memoryl State Machinesl Registers l Systemsl ADC and DAC l Arithmetic Combinational Logicl Exclusive-OR Gate (Dataflow style)l Exclusive-OR Gate (Beh

4、avioural style)l Exclusive-OR Gate (Structural style)l Miscell aneous Logic Gatesl Three-input Majority Voterl Magnitude Comparatorl Quad 2-input Nand (74x00)l BCD to Seven Segment Decoderl Dual 2-to-4 Decoderl Octal Bus Transceiverl Quad 2-input ORl 8-bit Identity Comparatorl Hamming Encoderl Hammi

5、ng Decoderl 2-to-4 Decoder with Testbench and Configurationl Multiplexer 16-to-4 using Selected Signal Assignment Statementl Multiplexer 16-to-4 using Conditional Signal Assignment Statement l Multiplexer 16-to-4 using if-then-elsif-else Statementl M68008 Address Decoderl Highest Priority Encoderl N

6、-input AND GateCountersh t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r s e w a r e / a d v e d a / v h d l / v hd l e x m p . h t m l ( 1 o f 6 7 ) 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 1 Examples of VHDL Descriptionsl Counter using a Conversion Functionl Generated Binary Up Counterl Counter

7、 using Multiple Wait Statementsl Synchronous Down Counter with Parallel Loadl Mod-16 Counter using JK Flip-flopsl Pseudo Random Bit Sequence Generatorl Universal Counter/Registerl n-Bit Synchronous CounterShift Registersl Universal Shift Register/Counterl TTL164 Shift Registerl Behavioural descripti

8、on of an 8-bit Shift Registerl Structural Description of an 8-bit Shift RegisterMemoryl ROM-based Waveform Generatorl A First-in First-out Memoryl Behavioural model of a 16-word, 8-bit Random Access Memory l Behavioural model of a 256-word, 8-bit Read Only Memory State Machinesl Classic 2-Process St

9、ate Machine and Test Benchl State Machine using Variablel State Machine with Asynchronous Resetl Pattern Detector FSM with Test Benchl State Machine with Moore and Mealy outputsl Moore State Machine with Explicit State encodingl Mealy State Machine with Registered Outputsl Moore State Machine with C

10、oncurrent Output Logic Systemsl Pelican Crossing Controllerl Simple Microprocessor Systeml Booth Multiplierl Lottery Number Generatorl Digital Delay Unitl Chess ClockADC and DACl Package defining a Basic Analogue typel 16-bit Analogue to Digital Converterl 16-bit Digital to Analogue Converterl 8-bit

11、 Analogue to Digital Converterl 8-bit Unipolar Successive Approximation ADCh t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r s e w a r e / a d v e d a / v h d l / v hd l e x m p . h t m l ( 2 o f 6 7 ) 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 7 Examples of VHDL DescriptionsArithmeticl 8-bit Unsig

12、ned Multiplierl n-bit Adder using the Generate Statementl A Variety of Adder Stylesl Booth MultiplierRegistersl Universal Registerl Octal D-Type Register with 3-State Outputsl Quad D-Type Flip-flopl 8-bit Register with Synchronous Load and ClearUniversal RegisterDescription - This design is a univer

13、sal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter. The register can be loaded from a set of parallel data inputsand the mode is controlled by a 3-bit input. The termcnt (terminal count) output goes high when the re

14、gister contains zero.LIBRARY ieee;USE ieee.Std_logic_1164.ALL;USE ieee.Std_logic_unsigned.ALL;ENTITY unicntr ISGENERIC(n : Positive := 8); -size of counter/shifterPORT(clock, serinl, serinr : IN Std_logic; -serial inputsmode : IN Std_logic_vector(2 DOWNTO 0); -mode controldatain : IN Std_logic_vecto

15、r(n-1) DOWNTO 0); -parallel inputsdataout : OUT Std_logic_vector(n-1) DOWNTO 0); -parallel outputstermcnt : OUT Std_logic); -terminal count outputEND unicntr;ARCHITECTURE v1 OF unicntr ISSIGNAL int_reg : Std_logic_vector(n-1) DOWNTO 0);BEGINmain_proc : PROCESSBEGINWAIT UNTIL rising_edge(clock);CASE

16、mode IS-resetWHEN 000 = int_reg 0);-parallel loadWHEN 001 = int_reg int_reg int_reg int_reg int_reg NULL;END CASE;END PROCESS;det_zero : PROCESS(int_reg) -detects when count is 0BEGINtermcnt = 1;FOR i IN int_regRange LOOPh t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r s e w a r e / a

17、 d v e d a / v h d l / v hd l e x m p . h t m l ( 3 o f 6 7 ) 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 Examples of VHDL DescriptionsIF int_reg(i) = 1 THENtermcnt = 0;EXIT;END IF;END LOOP;END PROCESS;-connect internal register to dataout portdataout = int_reg;END v1;Octal D-Type Register with 3-State OutputsS

18、imple model of an Octal D-type register with three-state outputs using two concurrent statements.LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY ttl374 ISPORT(clock, oebar : IN std_logic;data : IN std_logic_vector(7 DOWNTO 0);qout : OUT std_logic_vector(7 DOWNTO 0);END ENTITY ttl374;ARCHITECTURE usi

19、ng_1164 OF ttl374 IS-internal flip-flop outputsSIGNAL qint : std_logic_vector(7 DOWNTO 0);BEGINqint = data WHEN rising_edge(clock); -d-type flip flopsqout = qint WHEN oebar = 0 ELSE ZZZZZZZZ; -three-state buffers END ARCHITECTURE using_1164; Exclusive-OR Gate (Dataflow style)- 2 input exclusive or-

20、Modeled at the RTL level. entity x_or isport (in1 : in bit ;in2 : in bit ;out1 : out bit);end x_or;architecture rtl of x_or isbeginout1 = in1 xor in2 after 10 ns;end rtl;Exclusive-OR Gate (Behavioural style)- Exclusive or gate- modeled at the behavioral level.entity x_or isport (in1 : in bit ;in2 :

21、in bit ;out1 : out bit) ;end x_or;architecture behavior of x_or ish t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r s e w a r e / a d v e d a / v h d l / v hd l e x m p . h t m l ( 4 o f 6 7 ) 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 Examples of VHDL Descriptionsbeginprocess(in1, in2)beginif in

22、1 = in2 thenout1 = 0 after 10 ns;else out1 = 1 after 10 ns;end if;end process;end behavior;Exclusive-OR Gate (Structural style)- 2 input exclusive-or gate.- Modeled at the structural level. entity x_or isport (in1 : in bit ;in2 : in bit ;out1 : out bit) ;end x_or;entity and_gate isport (a : in bit ;

23、b : in bit ;c : out bit) ;end and_gate;architecture behavior of and_gate isbeginprocess(a,b)beginc = a and b after 5 ns;end process;end behavior;entity or_gate isport (d : in bit ;e : in bit ;f : out bit) ;end or_gate;architecture behavior of or_gate isbeginprocess(d,e)beginf = d or e after 4 ns;end

24、 process;end behavior;entity inverter isport (g : in bit ;h : out bit) ;end inverter;architecture behavior of inverter isbeginprocess(g)beginh t1, b = in2, c = t3);u1: and_gate port map ( a = in1, b = t2, c = t4);u2: inverter port map ( g = in1, h = t1);u3: inverter port map ( g = in2, h = t2);u4: o

25、r_gate port map ( d = t3, e = t4, f = out1);end structural;Three-input Majority VoterThe entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.ENTITY maj ISPORT(a,b,c : IN BIT; m : OUT BIT);END maj;-Dataflow style architectureARCHITE

26、CTURE concurrent OF maj ISBEGIN-selected signal assignment statement (concurrent)WITH a&b&c SELECTm = 1 WHEN 110|101|011|111,0 WHEN OTHERS; END concurrent;-Structural style architectureARCHITECTURE structure OF maj IS-declare components used in architectureCOMPONENT and2 PORT(in1, in2 : IN BIT; out1

27、 : OUT BIT);END COMPONENT;COMPONENT or3 PORT(in1, in2, in3 : IN BIT; out1 : OUT BIT);END COMPONENT;-declare local signalsSIGNAL w1, w2, w3 : BIT;BEGIN-component instantiation statements.-ports of component are mapped to signals-within architecture by position.gate1 : and2 PORT MAP (a, b, w1);gate2 :

28、 and2 PORT MAP (b, c, w2);gate3 : and2 PORT MAP (a, c, w3);gate4 : or3 PORT MAP (w1, w2, w3, m);h t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r s e w a r e / a d v e d a / v h d l / v hd l e x m p . h t m l ( 6 o f 6 7 ) 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 Examples of VHDL DescriptionsEN

29、D structure;-Behavioural style architecture using a look-up table ARCHITECTURE using_table OF maj ISBEGINPROCESS(a,b,c)CONSTANT lookuptable : BIT_VECTOR(0 TO 7) := 00010111;VARIABLE index : NATURAL;BEGINindex := 0; -index must be cleared each time process executes IF a = 1 THEN index := index + 1; E

30、ND IF;IF b = 1 THEN index := index + 2; END IF;IF c = 1 THEN index := index + 4; END IF;m ,).Second architecture shows sequential behaviour -description.Both descriptions do not fully model behaviour of real -device for all possible combinations of inputs. ENTITY mag4comp ISGENERIC(eqdel,gtdel,ltdel

31、 : TIME := 10 ns); -output delay parametersPORT(a,b : IN BIT_VECTOR(3 DOWNTO 0); -input words, DOWNTO ordering needed for comparison operatorsaeqbin,agtbin,altbin : IN BIT; -expansion inputsaeqbout,agtbout,altbout : OUT BIT); -outputsEND mag4comp;ARCHITECTURE dataflow OF mag4comp IS-this architectur

32、e assumes that only one of the expansion inputs -is active at any time,if more than one expansion input is active, -more than one output may be active.BEGINaeqbout = 1 AFTER eqdel WHEN (a = b) AND (aeqbin = 1)ELSE 0 AFTER eqdel;agtbout b) OR (a = b) AND (agtbin = 1)ELSE 0 AFTER gtdel;altbout = 1 AFT

33、ER ltdel WHEN (a b) THENagtbout = 1 AFTER gtdel;aeqbout = 0 AFTER eqdel;altbout = 0 AFTER ltdel;ELSIF (a b) THENaltbout = 1 AFTER ltdel;aeqbout = 0 AFTER eqdel;agtbout = 0 AFTER gtdel;ELSE -a=b,expansion inputs have priority orderingIF (aeqbin = 1) THENaeqbout = 1 AFTER eqdel;agtbout = 0 AFTER gtdel

34、;altbout = 0 AFTER ltdel;ELSIF (agtbin = 1) THENagtbout = 1 AFTER gtdel;altbout = 0 AFTER ltdel;h t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r s e w a r e / a d v e d a / v h d l / v hd l e x m p . h t m l ( 7 o f 6 7 ) 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 Examples of VHDL Descriptionsae

35、qbout = 0 AFTER eqdel;ELSIF (altbin = 1) THENagtbout = 0 AFTER gtdel;altbout = 1 AFTER ltdel;aeqbout = 0 AFTER eqdel;ELSEagtbout = 0 AFTER gtdel;altbout = 0 AFTER ltdel;aeqbout = 0 AFTER eqdel;END IF;END IF;END PROCESS;END behaviour;8-bit Register with Synchronous Load and ClearThe design entity sho

36、ws the standard way of describing a register using a synchronous process, ie. a process containing a single wait statement which is triggered by a rising edge on the clock input.library ieee;use ieee.std_logic_1164.all;entity reg8 isport(clock, clear, load : in std_logic;d : in std_logic_vector(7 do

37、wnto 0);q : out std_logic_vector(7 downto 0);end entity reg8;architecture v1 of reg8 isbeginreg_proc : processbeginwait until rising_edge(clock);if clear = 1 thenq 0);elsif load = 1 thenq = d;end if;end process;end architecture v1;BCD to Seven Segment DecoderThe use of the std_logic literal - (dont

38、care) is primarily for the synthesis tool. This example illustrates the use of the selected signal assignment.LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY seg7dec ISPORT(bcdin : IN std_logic_vector(3 DOWNTO 0);segout : OUT std_logic_vector(6 DOWNTO 0);END seg7dec;ARCHITECTURE ver3 OF seg7dec ISBE

39、GINWITH bcdin SELECTsegout = 1000000 WHEN X0,1100111 WHEN X1,1101101 WHEN X2,0000011 WHEN X3,0100101 WHEN X4,0001001 WHEN X5,0001000 WHEN X6,1100011 WHEN X7,0000000 WHEN X8,h t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r s e w a r e / a d v e d a / v h d l / v hd l e x m p . h t m l

40、( 8 o f 6 7 ) 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 Examples of VHDL Descriptions0000001 WHEN X9,- WHEN OTHERS;END ver3;2-to-4 Decoder with Testbench and ConfigurationThis set of design units illustrates several features of the VHDL language including:l Using generics to pass time delay v alues to design

41、entities.l Design hierarchy using instantiated components.l Test benches for design verification.l Configuration declaration for binding components to design entities and setting delay v alues.-ANATOMY OF A VHDL MODEL-This VHDL source description illustrates the use-of the basic constructs of VHDL.-

42、The model describes a 2-input/4-output decoder-comprising two behavioural primitives inv and and3 -instanced in a structure.-ENTITY inv ISGENERIC(tplh,tphl,tplhe,tphle : TIME := 1 ns);PORT(a : IN BIT; b : OUT BIT);END inv;ARCHITECTURE behaviour OF inv ISBEGINPROCESS(a)VARIABLE state : BIT;BEGINstate

43、 := NOT(a);IF state = 1 THENb = state AFTER (tplh + tplhe);ELSEb = state AFTER (tphl + tphle);END IF;END PROCESS;END behaviour;-ENTITY and3 ISGENERIC(tplh,tphl,tplhe,tphle : TIME := 1 ns);PORT(a1,a2,a3 : IN BIT; o1 : OUT BIT);END and3;ARCHITECTURE behaviour OF and3 ISBEGINPROCESS(a1,a2,a3)VARIABLE s

44、tate : BIT;BEGINstate := a1 AND a2 AND a3;IF state = 1 THENo1 = state AFTER (tplh + tplhe);ELSEo1 = state AFTER (tphl + tphle);END IF;END PROCESS;END behaviour;-ENTITY dec2to4 ISPORT(s0,s1,en : IN BIT; y0,y1,y2,y3 : OUT BIT);END dec2to4;ARCHITECTURE structural OF dec2to4 ISCOMPONENT invh t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r s e w a r e / a d v e d a / v h d l / v hd l e x m p . h t m l ( 9 o f 6 7 ) 2 3 / 1 /