MIPS指令多周期CPU设计

1、 一、单周期CPU性能分析 二、 MIPS指令多周期CPU设计4.4 MIPS指令多周期CPU设计一、单周期一、单周期CPU性能分析性能分析SignImmCLKARDInstructionMemory+4A1A3WD3RD2RD1WE3A2CLKSign ExtendRegisterFile0101ARDDataMemoryWDWE01PC01PCInstr25:2120:1615:05:0SrcB20:1615:112+ALUResultReadDataWriteDataSrcAPCPlus4PCBranchWriteReg4:0Result31:26RegDstBranchMemWrite

2、MemtoRegALUSrcRegWriteOpFunctControlUnitZeroPCSrcCLKALUControl2:0ALU1010010100完整的单周期完整的单周期CPU结构结构单周期单周期CPU特点特点优点每条指令占用一个CPU周期逻辑设计简单，时钟设计也简单缺点各组成部件的利用率不高各部件大部分时间在保持信号时钟周期将满足执行时间最长指令的要求Load指令CPI =1 假定某单周期CPU各主要部件的延迟为：存储器（Memory）：2ns运算器（ALU/Adder）：2ns寄存器组（Register File）：1ns 指令周期比较长 所有指令都必须使用最长的周期假设某单周期

3、CPU，执行100条指令:25%的Load指令10%的Store指令45%的算逻指令20%的跳转指令单周期的执行时间 100*8 = 800ns可能的优化25*8+10*7+45*6+20*5=640nsSpeedup=800/640=1.25单周期单周期CPU其他问题其他问题 事实上，指令和数据都保存在同一个存储器中； 许多部件保持数据的时间过长，无法复用。例如， Adder 是否可以利用ALU？SignImmCLKARDInstructionMemory+4A1A3WD3RD2RD1WE3A2CLKSign ExtendRegisterFile0101ARDDataMemoryWDWE01

4、PC01PCInstr25:2120:1615:05:0SrcB20:1615:112+ALUResultReadDataWriteDataSrcAPCPlus4PCBranchWriteReg4:0Result31:26RegDstBranchMemWriteMemtoRegALUSrcRegWriteOpFunctControlUnitZeroPCSrcCLKALUControl2:0ALU1010010100二、二、 MIPS指令多周期指令多周期CPU设计设计多周期数据通路设计构思 在组合逻辑中插入寄存器，切分数据通路 大组合逻辑被切分为若干小组合逻辑 大延迟变为多个分段小延迟 不同指令

5、执行占用不同的功能单元（不必5个环节都走完）PCinstructionmemory+4RegisterFilertrsrdDatamemoryimmMUXMIPS指令多周期指令多周期CPU控制器设计思路控制器设计思路确定数据通路划分指令执行步骤指令流程图安排每条指令每个步骤的功能,并给出相应的控制信号指令流程表为指令执行步骤设计状态机为每个步骤的控制信号设计控制信号生成逻辑MIPS计算机硬件系统组成计算机硬件系统组成由由存储器存储器、寄存器堆寄存器堆、ALU部件部件、控制部件控制部件 4部分组成部分组成控制部件控制部件由由节拍发生器节拍发生器 和和 控制信号产生线路控制信号产生线路 组成，分别

6、完成标组成，分别完成标明明指令执行步骤指令执行步骤和向各个部件和向各个部件提供控制信号提供控制信号的功能。的功能。存储器存指令和数据存储器存指令和数据。 读指令时由读指令时由 PC 提供地址，读出的指令保存到提供地址，读出的指令保存到 IR；读写数据时由读写数据时由结果寄存器结果寄存器提供地址，提供地址，读操作读操作的读出数据保存到的读出数据保存到 DR;写操作写操作的写入数据由的写入数据由 B寄存器寄存器给出。给出。寄存器堆由寄存器堆由32个寄存器组成，可以用个寄存器组成，可以用N1(rs)、N2 (rt)同时读出两个寄存器的内同时读出两个寄存器的内容，分别存于容，分别存于A、B寄存器寄存器

7、; 可以用可以用 ND (rd 或或 rt ) 把把 DI 端的数据写入端的数据写入;被写入数据来自被写入数据来自结果寄存器结果寄存器 或或 DR。ALU完成算术和逻辑运算，两路输入分别为完成算术和逻辑运算，两路输入分别为A和和 B，其中，其中A路输入路输入可选择可选择 A寄存寄存器器或或 PC，B路输入路输入可选择可选择 B寄存器寄存器或或常数常数4、IR.immediate经符号扩展经符号扩展或或扩展扩展后又左移两位的值。后又左移两位的值。 ALU的运算数据：的运算数据：A OP BA OP 扩展的扩展的ImmePC + 4PC + 扩展的扩展的Imme4MIPS的的 ADD 指令指令 的

8、执行过程的执行过程译码译码周期周期： A rs B rt 取指取指 IRMEMPC 周期周期： PC PC+4执行执行 C A+B 周期周期：写回写回 寄存器堆寄存器堆rd C 周期周期：R型指令的实现型指令的实现(ADD)取指令IODR=0, ALUsrcA=0, ALUsrcB=01,ALUop=00, PCsrc=00MEMread, IRwrite, PCwrite译码/取操作数ALUsrcA=0, ALUsrcB=11,ALUop=00执行运算ALUsrcA=0, ALUsrcB=00,ALUop=00写回寄存器RegDST=1 RegWrite MemtoReg = 0MIPS的的

9、 LW 指令指令 的执行过程的执行过程译码译码周期周期：A rs取指取指 IRMEMPC 周期周期： PC PC+4执行执行 C A+ 扩展扩展imm 周期周期：内存内存 DRMEMC 周期周期：写回写回 寄存器堆寄存器堆rtDR 周期：周期：MIPS的的 BEQ 指令指令 的执行过程的执行过程取指取指 IRMEMPC 周期周期： PC PC+4执行执行 C A-B 周期周期： PC结果寄存器结果寄存器译码译码周期周期： 结果寄存器结果寄存器PC +SignExt( imm )MIPS的的 J 指令指令 的执行过程的执行过程译码译码周期周期： PC PC31.28 target 2 取指取指

10、IRMEMPC 周期周期： PC PC+4Branch型型Lw指令指令Sw指令指令 R 类型类型 J 指令指令 IRMEMPCPC PC+4SifSidSexeSmemSwb J指指令令 非非 J 指令指令Branch指令指令SW指令指令LW指令指令SW / LW指令指令非非 Branch / SW / LW指令指令指令步骤指令步骤 读取指令读取指令 指令译码指令译码 执行运算执行运算 内存读写内存读写 数据写回数据写回CA op B CA + 符符号扩展号扩展(Imm)若条件成立若条件成立则则 PCR状态转移图和指令各执行步骤的操作功能状态转移图和指令各执行步骤的操作功能PCPC31.28(

11、target2)MemCBRegrdCDRMemCRegrtDRCPC+(符号扩展符号扩展(imm)2)取指周期取指周期译码周期译码周期执行周期执行周期访存周期访存周期写回周期写回周期ARegrsBRegrtControl UnitALUSrcAPCSrcBranchALUSrcB1:0Opcode5:0ControlUnitALUControl2:0Funct5:0MainController(FSM)ALUOp1:0ALUDecoderRegWritePCWriteIorDMemWriteIRWriteRegDstMemtoRegRegisterEnablesMultiplexerSele

12、ctsMain Controller FSM: FetchSignImmCLKARDInstr / DataMemoryA1A3WD3RD2RD1WE3A2CLKSign ExtendRegisterFile010101PC01PCInstr25:2120:1615:05:0SrcB20:1615:112ALUResultSrcAALUOut31:26RegDstBranchMemWriteMemtoRegALUSrcARegWriteOpFunctControlUnitZeroPCSrcCLKCLKALUControl2:0ALUWDWECLKAdr01DataCLKCLKAB0001101

13、14CLKENENALUSrcB1:0IRWriteIorDPCWritePCEn0110XX0001010010ResetS0: FetchMain Controller FSM: FetchSignImmCLKARDInstr / DataMemoryA1A3WD3RD2RD1WE3A2CLKSign ExtendRegisterFile010101PC01PCInstr25:2120:1615:05:0SrcB20:1615:112ALUResultSrcAALUOut31:26RegDstBranchMemWriteMemtoRegALUSrcARegWriteOpFunctContr

14、olUnitZeroPCSrcCLKCLKALUControl2:0ALUWDWECLKAdr01DataCLKCLKAB000110114CLKENENALUSrcB1:0IRWriteIorDPCWritePCEn0110XX0001010010IorD = 0AluSrcA = 0ALUSrcB = 01ALUOp = 00PCSrc = 0IRWritePCWriteResetS0: FetchMain Controller FSM: DecodeIorD = 0AluSrcA = 0ALUSrcB = 01ALUOp = 00PCSrc = 0IRWritePCWriteResetS

15、0: FetchS1: DecodeSignImmCLKARDInstr / DataMemoryA1A3WD3RD2RD1WE3A2CLKSign ExtendRegisterFile010101PC01PCInstr25:2120:1615:05:0SrcB20:1615:112ALUResultSrcAALUOut31:26RegDstBranchMemWriteMemtoRegALUSrcARegWriteOpFunctControlUnitZeroPCSrcCLKCLKALUControl2:0ALUWDWECLKAdr01DataCLKCLKAB000110114CLKENENAL

16、USrcB1:0IRWriteIorDPCWritePCEnX000XX0XXXXXXX00Main Controller FSM: Address CalculationIorD = 0AluSrcA = 0ALUSrcB = 01ALUOp = 00PCSrc = 0IRWritePCWriteResetS0: FetchS2: MemAdrS1: DecodeOp = LWorOp = SWSignImmCLKARDInstr / DataMemoryA1A3WD3RD2RD1WE3A2CLKSign ExtendRegisterFile010101PC01PCInstr25:2120:

17、1615:05:0SrcB20:1615:112ALUResultSrcAALUOut31:26RegDstBranchMemWriteMemtoRegALUSrcARegWriteOpFunctControlUnitZeroPCSrcCLKCLKALUControl2:0ALUWDWECLKAdr01DataCLKCLKAB000110114CLKENENALUSrcB1:0IRWriteIorDPCWritePCEnX000XX0110010X00Main Controller FSM: Address CalculationIorD = 0AluSrcA = 0ALUSrcB = 01A

18、LUOp = 00PCSrc = 0IRWritePCWriteALUSrcA = 1ALUSrcB = 10ALUOp = 00ResetS0: FetchS2: MemAdrS1: DecodeOp = LWorOp = SWSignImmCLKARDInstr / DataMemoryA1A3WD3RD2RD1WE3A2CLKSign ExtendRegisterFile010101PC01PCInstr25:2120:1615:05:0SrcB20:1615:112ALUResultSrcAALUOut31:26RegDstBranchMemWriteMemtoRegALUSrcARe

19、gWriteOpFunctControlUnitZeroPCSrcCLKCLKALUControl2:0ALUWDWECLKAdr01DataCLKCLKAB000110114CLKENENALUSrcB1:0IRWriteIorDPCWritePCEnX000XX0110010X00Main Controller FSM: lwIorD = 0AluSrcA = 0ALUSrcB = 01ALUOp = 00PCSrc = 0IRWritePCWriteALUSrcA = 1ALUSrcB = 10ALUOp = 00IorD = 1ResetS0: FetchS2: MemAdrS1: D

20、ecodeS3: MemReadOp = LWorOp = SWOp = LWRegDst = 0MemtoReg = 1RegWriteS4: MemWritebackMain Controller FSM: swIorD = 0AluSrcA = 0ALUSrcB = 01ALUOp = 00PCSrc = 0IRWritePCWriteALUSrcA = 1ALUSrcB = 10ALUOp = 00IorD = 1IorD = 1MemWriteResetS0: FetchS2: MemAdrS1: DecodeS3: MemReadS5: MemWriteOp = LWorOp =

21、SWOp = LWOp = SWRegDst = 0MemtoReg = 1RegWriteS4: MemWritebackMain Controller FSM: R-TypeIorD = 0AluSrcA = 0ALUSrcB = 01ALUOp = 00PCSrc = 0IRWritePCWriteALUSrcA = 1ALUSrcB = 10ALUOp = 00IorD = 1RegDst = 1MemtoReg = 0RegWriteIorD = 1MemWriteALUSrcA = 1ALUSrcB = 00ALUOp = 10ResetS0: FetchS2: MemAdrS1:

22、 DecodeS3: MemReadS5: MemWriteS6: ExecuteS7: ALUWritebackOp = LWorOp = SWOp = R-typeOp = LWOp = SWRegDst = 0MemtoReg = 1RegWriteS4: MemWritebackMain Controller FSM: beqIorD = 0AluSrcA = 0ALUSrcB = 01ALUOp = 00PCSrc = 0IRWritePCWriteALUSrcA = 0ALUSrcB = 11ALUOp = 00ALUSrcA = 1ALUSrcB = 10ALUOp = 00Io

23、rD = 1RegDst = 1MemtoReg = 0RegWriteIorD = 1MemWriteALUSrcA = 1ALUSrcB = 00ALUOp = 10ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCSrc = 1BranchResetS0: FetchS2: MemAdrS1: DecodeS3: MemReadS5: MemWriteS6: ExecuteS7: ALUWritebackS8: BranchOp = LWorOp = SWOp = R-typeOp = BEQOp = LWOp = SWRegDst = 0MemtoReg = 1Re

24、gWriteS4: MemWritebackComplete Multicycle Controller FSMIorD = 0AluSrcA = 0ALUSrcB = 01ALUOp = 00PCSrc = 0IRWritePCWriteALUSrcA = 0ALUSrcB = 11ALUOp = 00ALUSrcA = 1ALUSrcB = 10ALUOp = 00IorD = 1RegDst = 1MemtoReg = 0RegWriteIorD = 1MemWriteALUSrcA = 1ALUSrcB = 00ALUOp = 10ALUSrcA = 1ALUSrcB = 00ALUO

25、p = 01PCSrc = 1BranchResetS0: FetchS2: MemAdrS1: DecodeS3: MemReadS5: MemWriteS6: ExecuteS7: ALUWritebackS8: BranchOp = LWorOp = SWOp = R-typeOp = BEQOp = LWOp = SWRegDst = 0MemtoReg = 1RegWriteS4: MemWritebackMain Controller FSM: addiIorD = 0AluSrcA = 0ALUSrcB = 01ALUOp = 00PCSrc = 0IRWritePCWriteA

26、LUSrcA = 0ALUSrcB = 11ALUOp = 00ALUSrcA = 1ALUSrcB = 10ALUOp = 00IorD = 1RegDst = 1MemtoReg = 0RegWriteIorD = 1MemWriteALUSrcA = 1ALUSrcB = 00ALUOp = 10ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCSrc = 1BranchResetS0: FetchS2: MemAdrS1: DecodeS3: MemReadS5: MemWriteS6: ExecuteS7: ALUWritebackS8: BranchOp = L

27、WorOp = SWOp = R-typeOp = BEQOp = LWOp = SWRegDst = 0MemtoReg = 1RegWriteS4: MemWritebackOp = ADDIS9: ADDIExecuteS10: ADDIWritebackMain Controller FSM: addiIorD = 0AluSrcA = 0ALUSrcB = 01ALUOp = 00PCSrc = 0IRWritePCWriteALUSrcA = 0ALUSrcB = 11ALUOp = 00ALUSrcA = 1ALUSrcB = 10ALUOp = 00IorD = 1RegDst

28、 = 1MemtoReg = 0RegWriteIorD = 1MemWriteALUSrcA = 1ALUSrcB = 00ALUOp = 10ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCSrc = 1BranchResetS0: FetchS2: MemAdrS1: DecodeS3: MemReadS5: MemWriteS6: ExecuteS7: ALUWritebackS8: BranchOp = LWorOp = SWOp = R-typeOp = BEQOp = LWOp = SWRegDst = 0MemtoReg = 1RegWriteS4: Me

29、mWritebackALUSrcA = 1ALUSrcB = 10ALUOp = 00RegDst = 0MemtoReg = 0RegWriteOp = ADDIS9: ADDIExecuteS10: ADDIWritebackControl FSM: jIorD = 0AluSrcA = 0ALUSrcB = 01ALUOp = 00PCSrc = 00IRWritePCWriteALUSrcA = 0ALUSrcB = 11ALUOp = 00ALUSrcA = 1ALUSrcB = 10ALUOp = 00IorD = 1RegDst = 1MemtoReg = 0RegWriteIorD = 1MemWriteALUSrcA = 1ALUSrcB = 00ALUOp = 10ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCSrc = 01BranchResetS0: FetchS2: MemAdrS1: DecodeS3: MemRe