EDA课程设计乒乓球游戏机vhd语言l

1、目 录1 项目名称、内容与要求 04页1.1 设计内容04页1.2 具体要求04页2 系统整体架构（Architecture Description） 04页2.1 设计思路04页2.2 系统原理（包含：框图等阐述与设计说明等内容）04页3 系统设计 (含HDL或原理图输入设计)05页3.1 HDL 代码05页3.2 系统整体电路图（或RTL级电路图）12页4 系统仿真（Simulation Waveform）13页5FPGA实现（FPGA Implementation） 14页6 总结（Closing）16页参考书目（Reference）：16页一、项目名称、内容与要求二、系统整体架构（Ar

2、chitecture Description）2.1设计思路 根据系统设计的要求，乒乓球比赛游戏机的电路原理框图如下：三、系统设计 (含HDL或原理图输入设计)3.1 VHDL 代码比赛模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all; -引用必要的库函数和包集合entity compete is -实体名为pingpong port(reset:in std_logic;clk_1:in std_logic;startbutton:in

3、 std_logic; -开始游戏输入端口serve:in std_logic_vector(1 downto 0); -发球输入端口hit1,hit2，hit11，hit22:in std_logic; -甲和乙的击球输入端口light:out std_logic_vector(1 to 8); sound:out std_logic;-控制8个发光二极管的输出端口music_begin:out std_logic;-控制音乐开始的输出端口counta,countb，countc,countd,counte,countf:out std_logic_vector(3 downto 0); -

4、2个用于控制4个7段译码器的输出端口end compete;architecture one of compete istype pingpong is (waitserve,light1on,ballmoveto2,allow2hit,light8on,ballmoveto1,allow1hit);-设置7个状态，为枚举数据类型，记为pingpong signal state:pingpong;signal i:integer range 0 to 8;signal count1,count2,count3,count4,count5,count6:std_logic_vector(3 do

5、wnto 0):=0000; -内部计数器，是4位二进制变量beginprocess(clk_1) begin if(clk_1event and clk_1=1) then if count1=1 and count5=1 or count2=1 and count6=1 then music_begin=1;end if; if(reset=1)then music_begin=0; end if; end if; end process; process(clk_1) -状态机进程 -clk_1作为敏感信号触发进程begin -进程开始if reset=1 then -异步置位i=0;c

6、ount1=0;count2=0;count5=0;count6=0;elsif clk_1event and clk_1=1 then -当处于时钟inclock上升沿时 if count1=10 thencount1=0;count5=1; elsif count1=1 and count5=1 then i=0;count1=0;count5=0;count3=count3+1;count2=0;count6=0;elsif count2=10 then count2=0;count6=1; elsif count2=1 and count6=1 theni=0;count1=0;cou

7、nt2=0;count4=count4+1;count5=0;count6=0; elsif count3=4 or count4=4 then i=9;music_begin=1;startbutton=0;elsif startbutton=0 theni=0;count1=0;count2=0;count3=0;count4=0;count5=0;count6 -进程处于等待发球状态case serve iswhen 01= i=1;state i=8;statei i=0;sound -进程处于第一盏灯亮状态i=2;if hit2=1 or hit22=1 theni=0;count1

8、=count1+1;sound=”1”state=waitserve; elsestate -进程处于第八盏灯亮状态i=7;if hit1=1 or hit11=”1” theni=0;count2=count2+1;sound=”1”;state=waitserve;elsestate -进程处于球向甲移动状态if hit1=1 theni=0;count2=count2+1;sound=”1”;state=waitserve;elsif i=2 then i=1;state=allow1hit;else i -进程处于球向乙移动状态if hit2=1theni=0;count1=count

9、1+1; sound=”1”;state=waitserve;elsif i=7 then i=8;state=allow2hit;else i -进程处于允许甲击球状态if hit1=1 then i=2;state=ballmoveto2;else count2=count2+1;i=0;sound=”1”;state=waitserve;end if; if hit11=1 then i=2;state=ballmoveto2;else count2=count2+1;i=0;sound=”1”;state -进程处于允许乙击球状态if hit2=1then i=7;state=ball

10、moveto1;else count1=count1+1;i=0;sound=”1”;state=waitserve;end if; if hit22=1then i=7;state=ballmoveto1;else count1=count1+1;i=0;sound=”1”;state=waitserve;end if;end case;end if;end if;end process;counta=count1;countb=count2;countc=count3;countd=count4;counte=count5;countf=count6; process(clk_1) if

11、(clk_1event and clk_1=1)then-进程处i信号控制发光二极管的亮暗light=10000000when(i=1) else01000000 when(i=2) else00100000 when(i=3) else00010000 when(i=4) else00001000 when(i=5) else00000100 when(i=6) else00000010 when(i=7) else00000001 when(i=8) else00000000;End process; -其他情况所有发光二极管都暗end one;分频模块library IEEE; use

12、IEEE.std_logic_1164.all;use ieee.std_logic_arith.all;use IEEE.std_logic_unsigned.all;entity division16 isport( cp:in std_logic; clk_4:out std_logic );end division16;architecture division_body of division16 issignal count:std_logic_vector(3 downto 0);beginprocess(cp)beginif(cpevent and cp=1)then if(c

13、ount=1111)thencount0);elsecount=count+1;end if;end if;end process;process(cp)beginif(cpevent and cp=1)then if(count=1111)thenclk_4=1;elseclk_4qqqqqqqqqqq=0000000; end case; end process; end disp_arc;数码管选择LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux2 IS PORT(a,b: IN STD_LOGIC_VECTOR(6 downto 0

14、);sel: IN STD_LOGIC;c:OUT STD_LOGIC_VECTOR(6 downto 0);END mux2;ARCHITECTURE example OF mux2 IS BEGIN PROCESS(sel) BEGINIF(SEL=1)THEN c=a;ELSE c=b;END IF;END PROCESS;END example;音乐模块（两只老虎）library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all;entity music is port ( music_begin:in

15、 std_logic; clk_4:in std_logic; clk:in std_logic; music_out:out std_logic ); end music;architecture music_body of music is constant m1:integer:=637;-955; constant m2:integer:=587;-851; constant m3:integer:=505;-758; constant m4:integer:=468;-716; constant m5:integer:=425;-639; constant m6:integer:=3

16、79;-569; constant m7:integer:=330;-506; constant m0:integer:=0; signal counter:integer range 0 to 67; signal count:integer range 0 to 1000; signal sub:integer range 0 to 1000; signal carrier:std_logic; signal pat,pat1,pat2:std_logic;beginprocess(clk) begin if(clkevent and clk=1)then if(carrier=1) th

17、en sub=count; else sub=sub-1; end if; end if; end process;process(sub) begin if(sub=0) then pat=1; else pat=0; end if; carrier=pat; end process; process(clk) begin if(clkevent and clk=1)then pat1=pat; end if; end process;process(pat1) begin if(pat1event and pat1=1) then pat2= not pat2; end if; music

18、_out=pat2; end process; process(clk_4) begin if(clk_4event and clk_4=1) then if(music_begin=1) then counter=counter+1; else countercountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcoun

19、tcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcountcount=m0; end case; end process; end music_body;3.2 系统整体电路图（或RTL级电路图）四、系统仿真（Simulation Waveform）功能仿真波形图时序仿真波形图 五、FPGA实现（FPGA Implementa