基础逻辑元件代码

1、module select_3(a,b,s,q);input a,b,s;output q;reg q;alwaysbegin q=s?a:b; end endmodule module santaimen(y,en,a); output reg y; input en,a; always begin if(en) y=a; else y=1bz; endendmodule module eight_3(y,x);output y;input 7:0x;reg 2:0 y;always(x)begincase(x7:0)8b10000000:y=3b000;8b01000000:y=3b001

2、;8b00100000:y=3b010;8b00010000:y=3b011;8b00001000:y=3b100;8b00000100:y=3b101;8b00000010:y=3b110;8b00000001:y=3b111;default:y=3b000;endcaseendendmodulemodule three_8yimaqi(Y,A,G1,G2,G3);output reg7:0 Y;input 2:0 A;input G1,G2,G3;always(A,G1,G2,G3)beginif(G1=0) Y=8b11111111;else if(G2=1) Y=8b11111111;

3、else if(G3=1) Y=8b11111111;else case(A2:0)3b000:Y=8b11111110;3b001:Y=8b11111101;3b010:Y=8b11111011;3b011:Y=8b11110111;3b100:Y=8b11101111;3b101:Y=8b11011111;3b110:Y=8b10111111;3b111:Y=8b01111111;default:Y=8bzzzzzzzz;endcaseendEndmodulemodule fourchooseone(y,w,a1,a2,en);output reg y;input 3:0 w;input

4、a1,a2,en;always(en,a1,a2)if(en=0) y=1b0;elsecase(a1,a2)2b00:y=w0;2b01:y=w1;2b10:y=w2;2b11:y=w3;default:y=1b0;endcaseEndmodulemodule banjiaqi(s,c,a,b);output s,c;input a,b;assign s=ab;assign c=a&b;Endmodulemodule quanjiaqi(s,c2,a,b,c1);output s,c2;input a,b,c1;assign s=(ab)c1;assign c2=(a&b)|(b&c2)|(

5、a&c2);Endmodulemodule quanjiaqi_1(s,co,a,b,ci);output s,co;input a,b,ci;assign co=(a&b)|(b&ci)|(a&ci);assign s=(ab)ci; endmodulemodule quanjiaqi_4(S,Cout,A,B,Cin);output 3:0S;output Cout;input 3:0 A,B;input Cin;quanjiaqi_1 q1(S0,CO1,A0,B0,Cin);quanjiaqi_1 q2(S1,CO2,A1,B1,CO1);quanjiaqi_1 q3(S2,CO3,A

6、2,B2,CO2);quanjiaqi_1 q4(S3,Cout,A3,B3,CO3);Endmodulemodule quanjianqi_1(d,co,a,b,ci);output d,co;input a,b,ci;assign co,d=a-b-ci;Endmodulemodule quanjianqi_4(D,CO,A,B,CI);output 3:0D;output CO;input 3:0A,B;input CI;assign CO,D=A-B-CI;endmodulemodule toupiaobiaojue_7(Y,I);output reg Y;input 6:0 I;re

7、g 2:0sum;integer k;always(*)beginsum=0;for (k=0;k7;k=k+1)if(Ik) sum=sum+1;if(sum2) Y=1b1;else Y=1b0;endEndmodulemodule chengfaqi_8(sum,a,b);output reg15:0 sum;input 7:0 a,b;integer k;always(*)beginsum=0;for(k=0;k8;k=k+1)if(bk) sum=sum+(ak);end Endmodulemodule rs_chufaqi(Q,QN,R,S);output reg Q,QN;inp

8、ut R,S;reg d,dn;always(*)begin d=(R&dn);dn=(S&d);Q=d;QN=dn;endEndmodulemodule rs_chufaqi(R,S,Q,Q);input wire R;input wire S;output wire Q;output wire Q;wire SYNTHESIZED_WIRE_0;wire SYNTHESIZED_WIRE_1;assign Q = SYNTHESIZED_WIRE_1;assign Q = SYNTHESIZED_WIRE_0;assign SYNTHESIZED_WIRE_1 = (SYNTHESIZED

9、_WIRE_0 & R);assign SYNTHESIZED_WIRE_0 = (S & SYNTHESIZED_WIRE_1);endmodulemodule jk_chufaqi(Q,QN,R,S,J,K,clk);output Q,QN;input R,S,J,K,clk;reg Q,QN;always(posedge clk)beginif(R,S=2b01) begin Q=0;QN=1;endelse if(R,S=2b10) beginQ=1;QN=0;endelse if(R,S=2b00) beginQ=Q;QN=QN;endelse if(R,S=2b11)beginca

10、se(J,K)2b00: begin Q=Q;QN=QN; end 2b01: begin Q=0;QN=1; end2b10: begin Q=1;QN=0; end2b11: begin Q=Q;QN=QN; endendcaseendendendmodulemodule Dchufaqi(Q,QN,R,S,CLK,D);output reg Q,QN;input R,S,CLK,D;always(posedge CLK)begin if(R,S=2b10) begin Q=1;QN=0;endelse if(R,S=2b01) begin Q=0;QN=1;endelse if(R,S=

11、2b11)if(D) begin Q=1;QN=0;endelsebegin Q=0;QN=1;endendendmodulemodule Tchufaqi(Q,CLK,T);output reg Q;input CLK,T;always(posedge CLK)beginif(T) Q=Q;else Q=Q;endendmodule module tongbujishu_4(Q,CO,R,S,CLK,D,EN);output reg 3:0Q;output reg CO;input R,S,CLK,EN;input 3:0D;always(posedge CLK or posedge R)b

12、eginif(R) begin Q=4b0000;CO=1b0; endelse if(S) begin Q=D;CO=1b0; endelse if(EN)beginQ=Q+1;if(Q=4b1111) CO=1b1;else CO=1b0;endelse begin Q=Q;CO=CO; endendEndmodulemodule jishuqi_24(co,one,ten,clk,reset);output co;reg co;output reg 3:0 one;output reg 3:0 ten;input clk,reset;always (posedge clk)begin i

13、f(reset) begin one=0;ten=0;co=1b0; end else if(ten,one=8b00100100) begin one=0;ten=0;co=1b1; end else if(one=4b1001) begin one=0;ten=ten+1;co=1b0; end else begin one=one+1;co=1b0; endendEndmodulemodule jishuqi_60(one,ten,co,data,set,clk,clear);output reg 3:0 one,ten;output reg co;input 7:0data;input

14、 set,clk,clear;always (posedge clk)begin if(clear) begin one=0;ten=0;co=0; end else if(set) begin ten,one=data; end else if(one=4b1001) begin if(ten=4b0101) begin one=0;ten=0;co=1b1; end else begin one=0;ten=ten+1;co=0; end end else begin one=one+1; endendEndmodulemodule jishuqi_60_biaozhun(q,co,dat

15、a,ci,start,set,reset,clk);output reg 7:0 q;output wire co;input 7:0data;input ci,start,set,reset,clk;always(posedge clk)beginif(reset) begin q=0;endelse if(set) begin q=data;endelse if(start)begin if(q3:0=4b1001) begin q3:0=0; if(q7:4=4b0101) begin q7:4=0; end else begin q7:4=q7:4+1; end end else be

16、gin q3:0=q3:0+1; end endendassign co=(q7:0=8b01011001)&start)?1:0;Endmodulemodule yibujishuqi(q,clk,reset);output reg 3:0q;input clk,reset;reg 3:0 qn;always(posedge clk)beginif(!reset) begin q0=0;qn0=1;endelse begin q0=q0;qn0=q0;endendalways(posedge qn0)beginif(!reset) begin q1=0;qn1=1;endelse begin

17、 q1=q1;qn1=q1;endendalways(posedge qn1)beginif(!reset) begin q2=0;qn2=1;endelse begin q2=q2;qn2=q2;endendalways(posedge qn2)beginif(!reset) begin q3=0;qn3=1;endelse begin q3=q3;qn3=q3;endendEndmodulemodule tongbujishuqi_jianfa(q,co,data,set,clk);output reg 3:0q;output wire co;input 3:0data;input set

18、,clk;always (posedge clk)beginif(set) begin q3:0=data3:0; endelse if(q3:0=4b0000) begin q3:0=4b1111; endelse q3:0=q3:0-1;endassign co=(q3:0=4b0000)?1:0;Endmodulemodule jishuqi_jiajian(q,co,data,clr,set,clk,start,jia);output reg3:0q;output reg co;input clr,set,clk,start,jia;input 3:0data;always(posed

19、ge clk)begin if(clr) q3:0=0; else if(set) q3:0=data3:0; else if(start) begin if(jia) begin if(q=4b1111) begin q=0;co=1;end else begin q=q+1;co=0;end end else begin if(q=4b0000) begin q=4b1111;co=1;end else begin q=q-1; co=1;end end end else q=q;endEndmodulemodule kebianjishuqi_x(q,clk,mo,clr,c);outp

20、ut reg 3:0q;input clk,clr,c;input 3:0mo;reg 3:0d;always (posedge clk)begind=mo-1;if(clr) q=0; else begin if(c) begin q=d;end else begin if(q=d) begin q=0; end else q=q+1; end endendEndmodulemodule jicunqi_8(q,data,oe,clk);output reg 7:0q;input 7:0data;input oe,clk;always (posedge clk)begin if(oe) q=

21、8bzzzzzzzz; else q=data;endEndmodulemodule suocunqi(q,data,c,oe);output reg 3:0q;input 3:0data;input c,oe;always (*)beginif(oe) q=bz;else if(c) q=data;endEndmodulemodule yiweijicunqi_zuoyou(q,data,zuo,clk);output reg 7:0q;input 7:0data;input zuo,clk;integer k;always(posedge clk)beginif(zuo) begin fo

22、r(k=0;k6;k=k+1) q0=b0; qk+1=datak; end else begin for(k=0;k6;k=k+1) q7=b0; qk=datak+1; endendEndmodulemodule yiweijicunqi_zuoyou(q_left,q_right,qin,clk,left);output reg q_left,q_right;input qin,clk,left;reg 6:0 data;integer k;always (posedge clk)begin if(left) begin data0=qin; for(k=1;k=6;k=k+1) dat

23、ak=datak-1; end else begin data60;k=k-1) datak-1=datak; end q_left=data6;q_right=data0; endEndmodulemodule siso4_1(q,clk,data);output reg q;input clk,data;reg3:0 z;integer i;always (posedge clk)begin z0=data; for(i=1;i=3;i=i+1) begin zi=zi-1; end q=z3;endEndmodulemodule sipo(dout,data,clk,clr);output reg 4:0dout;input data,clk,clr;always (posedge clk)begin if(clr) dout=0; else begin dout=dout