数字系统设计实验---32位串行加法器实验

1、深 圳 大 学 实 验 报 告 课程名称： 数字系统设计 实验项目名称： 32位串行加法器 学院： 信息工程学院 专业： 电子信息工程 指导教师： 报告人： 学号：20091000000 班级： 1班 实验时间： 2011-12-4 实验报告提交时间： 2011-12-10 教务处制一、实验目的与要求：实验目的：1、 掌握串行加法器的原理和设计。2、 熟悉VHDL状态机的设计。3、 学会分析波形图。实验要求：设计一个用一个1位加法器构建的一个32位串行加法器。重点是算法状态机的实现还有系统的时序分析；输出和整理VHDL源代码；输出和整理电路结构图；输出和整理仿真波形图二、实验原理1、设计原理图

2、：本图参考课本2、流程图：针对以上流程图，其中，Sh为控制移位寄存器的使能信号，k为工作状态指示信号，load为加载信号，counter为运算计数器，N为系统工作控制信号。从流程图中可以看出加法器的整个工作流程是怎么样子的，具体工作情况如下面的设计。三、实验内容与步骤1、VHDL代码的编写：-控制器-library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;entity controller is Port ( clk : in STD_LOGIC; N : in STD_LOGIC; K,Sh,load

3、: out STD_LOGIC);end controller;architecture Behavioral of controller issignal state,nextstate:integer range 0 to 2; -设置状态signal counter:std_logic_vector(4 downto 0);beginprocess(clk)beginif(clk'event and clk='1') thenstate<=nextstate; -上升沿触发启动end if;end process;process(clk,N)beginif(

4、clk'event and clk='1') thencase state is -设置各状态when 0 =>sh<='0'K<='0'load<='0'counter<="00000"if N='1' thenload<='1'nextstate<=1;else nextstate<=0;end if;when 1 =>sh<='1'K<='0'load<='

5、;0'if counter="11110" thencounter<=counter+1;nextstate<=2;else counter<=counter+1;nextstate<=1;end if;when 2 =>sh<='0'K<='1'load<='0'if N='0' thennextstate<=0;elsenextstate<=2;end if;end case;end if;end process;end Behaviora

6、l;-加数寄存器-library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity registers_jiashu is Port ( input : in STD_LOGIC_vector(31 downto 0); Sh,load,clk: in STD_LOGIC; SO : out STD_LOGIC);end registers_jiashu;architecture Behavioral of registers_jiashu issignal x:std_logic_vector(31 downto 0);beginprocess(clk)begi

7、nif(clk'event and clk='1') thenif (load='1') then x<=input; -输入放入寄存器elsif (sh='1') then -移位x(30 downto 0)<=x(31 downto 1);end if;end if;end process;so<=x(0);end Behavioral;-累加器-library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity registers_add is Port ( input : in STD

8、_LOGIC_vector(31 downto 0); clk : in STD_LOGIC; load,Sh,Si: in STD_LOGIC; SO : out STD_LOGIC; output:out std_logic_vector(31 downto 0);end registers_add;architecture Behavioral of registers_add issignal x:std_logic_vector(31 downto 0);beginprocess(clk)beginif(clk'event and clk='1') theni

9、f(load='1') thenx<=input;elsif(Sh='1') thenx(30 downto 0)<=x(31 downto 1); -移位x(31)<=Si;end if;end if;end process;So<=x(0);output<=x; -把最后值输出来end Behavioral;-全加器-library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity full_adder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; ci

10、n : in STD_LOGIC; s : out STD_LOGIC; cout : out STD_LOGIC);end full_adder;architecture Behavioral of full_adder isbegins<=a xor b xor cin;cout<=(a and b)or(a and cin) or (b and cin);end Behavioral;-D触发器-library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity DFF is Port ( D : in STD_LOGIC; clk : in ST

11、D_LOGIC; rst,CE : in STD_LOGIC; Q: out STD_LOGIC);end DFF;architecture Behavioral of DFF isbeginprocess(rst,clk,CE)beginif(rst='1') thenQ<='0'elsif CE='1' and (clk'event and clk='1') thenQ<=D;end if;end process;end Behavioral;-主函数-library IEEE;use IEEE.STD_L

12、OGIC_1164.ALL;entity adder_32 isport(inputA,inputB:in std_logic_vector(31 downto 0);clk,N :in std_logic;outputA:out std_logic_vector(31 downto 0);K:out std_logic);end adder_32;architecture Behavioral of adder_32 is -对各个元件进行例化- component controller is -控制器Port ( clk : in STD_LOGIC; N : in STD_LOGIC;

13、K,Sh,load : out STD_LOGIC);end component;component registers_jiashu is -加数寄存器 Port ( input : in STD_LOGIC_vector(31 downto 0); Sh,load,clk: in STD_LOGIC; SO : out STD_LOGIC);end component;component registers_add is - 累加器 Port ( input : in STD_LOGIC_vector(31 downto 0); clk : in STD_LOGIC; load,Sh,Si

14、: in STD_LOGIC; SO : out STD_LOGIC; output:out std_logic_vector(31 downto 0);end component;component full_adder is -全加器 Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; s : out STD_LOGIC; cout : out STD_LOGIC);end component;component DFF is -D触发器 Port ( D : in STD_LOGIC; clk : in STD_L

15、OGIC; rst,CE : in STD_LOGIC; Q: out STD_LOGIC);end component;signal Sh,load,Xi,Yi,Si,cin,sum,cout:std_logic; -中间变量beginA1: controller port map(clk,n,k,Sh,load);A2: registers_jiashu port map(inputB,Sh,load,clk,Yi);A3: registers_add port map(inputA,clk,load,Sh,sum,Xi,outputA);A4: full_adder port map(X

16、i,Yi,cin,sum,cout);A5: DFF port map (cout,clk,load,Sh,cin);end Behavioral;2、仿真代码的编写：LIBRARY ieee;USE ieee.std_logic_1164.ALL; ENTITY adder_32_testbench ISEND adder_32_testbench; ARCHITECTURE behavior OF adder_32_testbench IS - Component Declaration for the Unit Under Test (UUT) COMPONENT adder_32 PO

17、RT( inputA : IN std_logic_vector(31 downto 0); inputB : IN std_logic_vector(31 downto 0); clk : IN std_logic; N : IN std_logic; outputA : OUT std_logic_vector(31 downto 0); K : OUT std_logic ); END COMPONENT; -Inputs signal inputA : std_logic_vector(31 downto 0) := (others => '0'); signal

18、 inputB : std_logic_vector(31 downto 0) := (others => '0'); signal clk : std_logic := '0' signal N : std_logic := '0' -Outputs signal outputA : std_logic_vector(31 downto 0); signal K : std_logic; - Clock period definitions constant clk_period : time := 10 ns; BEGIN - Inst

19、antiate the Unit Under Test (UUT) uut: adder_32 PORT MAP ( inputA => inputA, inputB => inputB, clk => clk, N => N, outputA => outputA, K => K ); - Clock process definitions clk_process :process beginclk <= '0'wait for clk_period/2;clk <= '1'wait for clk_period

20、/2; end process; stim_proc: process begin-进行输入仿真 inputA<="00000000000000000000000001001001" - inputa= 73,inputB<="00000000000000000000000010001010" - inputb= 138,N<='1' -N=1时开始计时，并开始下载数据wait for 32*clk_period;-32个时钟周期之后N<='0' -N=0，停止数据下载，得出相加后的结果wait for 10*clk_period; - 延时10个时钟周期，进入下一轮仿真调试inputA<="01010101010101010101010101010101" - inputa= 1431655765,inputB<="00110000000000000000000010101000" -