循环冗余校验CRC模块设计EDA实验报告

1、EDA技术实验报告实验名称：循环冗余校验（CRC）模块设计姓名：xxx班级：xxxx学号：xxxxx实验日期：指导教师：一、 实验设计要求编译示例文件，给出仿真波形。建立一个新的设计，调入crcm模块。把其中的CRC校验生成模块和CRC校验查错模块连接在一起，协调工作。引出必要的信号，锁定引脚，并在EDA实验系统上实现。二、设计原理电路结构图或原理图：Crcm：Crcma：电路功能描述：把crcm模块的datacrco和datacrci连接起来，hrecv和hsend连接起来，输入有效数据后CRC校验生成模块对数据进行特殊运算，产生5位校验码，并和原数据并接成17位传输数据，CRC校验查错模块

2、取出传输数据后12位并对它进行同样的特殊运算，得到5位校验码，于传输数据钱5位比较，如果一样那么传输无误，不一样说明数据在传输途中错误了。三、实验程序程序一：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity crcm isport(clk,hrecv,datald,rst:in std_logic; sdata:in std_logic_vector(11 downto 0); datacrco:out std_logic_ve

3、ctor(16 downto 0); datacrci:in std_logic_vector(16 downto 0); rdata:out std_logic_vector(11 downto 0); datafini:out std_logic; error0,hsend:out std_logic);end crcm;architecture comm of crcm is constant multi_coef: std_logic_vector(5 downto 0) :="110101" signal cnt,rcnt:std_logic_vector(4 d

4、ownto 0); signal dtemp,sdatam,rdtemp:std_logic_vector(11 downto 0); signal rdatacrc:std_logic_vector(16 downto 0); signal st,rt:std_logic;beginprocess(rst,clk) variable crcvar :std_logic_vector(5 downto 0);beginif rst ='1' then st <='0' ; elsif(clk'event and clk ='1')t

5、hen if(st = '0' and datald ='1') then dtemp <= sdata;sdatam <= sdata;cnt <= (others=>'0'); hsend<='0' st<='1' elsif(st ='1' and cnt < 7) then cnt <= cnt + 1; if(dtemp(11)='1') then crcvar :=dtemp(11 downto 6)xor multi_co

6、ef; dtemp <= crcvar(4 downto 0) & dtemp(5 downto 0) & '0' else dtemp <= dtemp(10 downto 0) & '0'end if; elsif(st='1' and cnt=7)then datacrco<=sdatam & dtemp(11 downto 7); hsend <='1'cnt <=cnt + 1; elsif(st='1' and cnt =8) then hs

7、end <= '0'st <= '0' end if; end if;end process;process(rst,hrecv,clk) variable rcrcvar : std_logic_vector(5 downto 0);beginif rst ='1' then rt <='0' elsif(clk'event and clk ='1')then if(rt = '0' and hrecv ='1')then rdtemp <=data

8、crci(16 downto 5); rdatacrc <=datacrci;rcnt <=(others=>'0');error0<= '0'rt<='1' elsif(rt = '1' and rcnt<7)then datafini<='0'rcnt<=rcnt+1; if(rdtemp(11) = '1')then rcrcvar := rdtemp(11 downto 6)xor multi_coef; rdtemp<= rcrcvar

9、(4 downto 0) & rdtemp(5 downto 0) & '0' else rdtemp<= rdtemp(10 downto 0)&'0'end if; elsif(rt='1' and rcnt=7)then datafini<='1' rdata<=rdatacrc(16 downto 5); rt<='0' if(rdatacrc(4 downto 0)/=rdtemp(11 downto 7)then error0<='1'

10、;end if;end if;end if;end process;end comm;程序二：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity crcma isport (clk,datald,rst:in std_logic; sdata:in std_logic_vector(11 downto 0); rdata:out std_logic_vector(11 downto 0); error0:out std_logic

11、; datafini:out std_logic);end crcma;architecture comm of crcma iscomponent crcmport (clk,hrecv,datald,rst:in std_logic; sdata:in std_logic_vector(11 downto 0); datacrco:out std_logic_vector(16 downto 0); datacrci:in std_logic_vector(16 downto 0); rdata:out std_logic_vector(11 downto 0); datafini:out

12、 std_logic; error0,hsend:out std_logic);end component;signal datacrcp:std_logic_vector(16 downto 0);signal hsenp:std_logic;beginu1: crcm port map(rst=>rst,clk=>clk,sdata=>sdata,datald=>datald,datacrco=>datacrcp,hrecv=>hsenp,hsend=>hsenp,datacrci=>datacrcp,rdata=>rdata,erro

13、r0=>error0,datafini=>datafini);end architecture comm;四、编译及仿真结果选用器件型号、编译后使用器件资源情况、引脚配置情况（硬件实验）：时序分析结果（最大延时路径、最大时钟频率等等）：程序仿真波形图（结合文字分析仿真结果）：五、总结程序有点长，输入过程中注意漏字，漏符号。六、思考题library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity crcm isport(clk,hr

14、ecv,datald,rst:in std_logic; sdata:in std_logic_vector(11 downto 0); datacrco:out std_logic_vector(16 downto 0); datacrci:in std_logic_vector(16 downto 0); rdata:out std_logic_vector(11 downto 0); datafini:out std_logic; error0,hsend:out std_logic);end crcm;architecture comm of crcm is constant mult

15、i_coef: std_logic_vector(5 downto 0) :="110101" signal cnt,rcnt:std_logic_vector(4 downto 0); signal dtemp,sdatam,rdtemp:std_logic_vector(11 downto 0); signal rdatacrc:std_logic_vector(16 downto 0); signal st,rt:std_logic;beginprocess(rst,clk) variable crcvar :std_logic_vector(5 downto 0);

16、beginif rst ='1' then st <='0' ; elsif(clk'event and clk ='1')then if(st = '0' and datald ='1') then dtemp <= sdata;sdatam <= sdata;cnt <= (others=>'0'); hsend<='0' st<='1' elsif(st ='1' and cnt < 7)

17、then cnt <= cnt + 1; if(dtemp(11)='1') then crcvar :=dtemp(11 downto 6)xor multi_coef; dtemp <= crcvar(4 downto 0) & dtemp(5 downto 0) & '0' else dtemp <= dtemp(10 downto 0) & '0'end if; elsif(st='1' and cnt=7)then datacrco<=sdatam & dtemp(

18、11 downto 7); hsend <='1'cnt <=cnt + 1; elsif(st='1' and cnt =8) then hsend <= '0'st <= '0' end if; end if;end process;process(rst,hrecv,clk) variable rcrcvar : std_logic_vector(5 downto 0);beginif rst ='1' then rt <='0' elsif(clk'event and clk ='1')then if(rt = '0' and hrecv ='1')then rdtemp <=datacrci(16 downto 5); rdatacrc <=datacrci;r