ASIC设计流程课件

1、ASIC设计流程ASIC设计流程 2001年8月16日ASIC设计流程1. 可行性研究 2. 系统设计 3. 模块设计 4. 系统整合 5. 验证 6. 预布局布线 7. 后仿真 8. 布局布线 9. 流片 10. 测试11. 量产 ASIC设计流程1.1. 可行性研究可行性研究市场 成本 设计能力ASIC设计流程1.1 1.1 设计能力设计能力设计人员 数字电路 模拟电路 混合电路软硬件ASIC设计流程2.系统设计设计方式 功能设计 模块划分 ASIC设计流程2.1 2.1 设计方式设计方式自主开发 产品替代 FPGA转换 ASIC设计流程2.2 2.2 功能设计功能设计ZPC01芯片： 1

2、网同步功能 2系统定时功能 3RF控制功能 4QPSK Modem控制接口功能 5网络接口功能 6DSP接口功能 7基带数据收发功能 8CPU接口功能 9测试支持功能 ASIC设计流程2.3 2.3 模块划分模块划分ZPC01芯片的模块： 1 BOOTDEC 2 DSPDECREG 3 QPSKCLOCK 4 TIMING 5 UINT 6 QPSKSR 7 ADSAMPLE 8 CPUDECREG 9 RECRFPLL 10 TEST ASIC设计流程3. 3. 模块设计模块设计 电路设计代码实现功能验证电路综合综合后的功能验证ASIC设计流程3.1 3.1 电路设计电路设计功耗电路面积可测

3、性ASIC设计流程3.1.1 3.1.1 功耗功耗通过适当的电路设计，可以减小电路的功耗。123456ABCD654321DCBATitleNumberRevisionSizeBDate:24-Apr-2001Sheet of File:C:tankeminPHScktADSAMPLE.ddbDrawn By:CNT_3M84_eq4ResetnCLK_19M2ADCS_nADRD_nSAMPLE_OUT10Q2Q0Q13b100WRADDR_ADDRSTQDCLKRSTQDCLKRSTQDCLKRSTQDCLKRSTQDCLKRSTQDCLKRSTQDCLKASIC设计流程3.1.2 3.1

4、.2 电路面积电路面积尽量调用加工厂家的宏单元 在保证逻辑的情况下，尽量简化电路。ASIC设计流程3.1.3 3.1.3 可测性可测性扫描链 计数器1234ABCD4321DCBATitleNumberRevisionSizeA4Date:27-Apr-2001Sheet of File:C:zhaobozpc01_0410ZPC01.DdbDrawn By:Slot1_6_06:0Slot2_6_06:0Slot3_6_06:0Slot4_6_06:0RST_DELAYCNT_20min(18 BIT)CLK_19M2001CLK_150RST_CNTCPU_FailnCNT_10min17

5、:5CNT_10min17:018d20010013d62501CNT_7ms(17 BIT)WatchReset010117h1fffe18h3fffeTest_modeRST_DELAY_GATERST_CNT_GATERSTQDCLKRSTQDCLKSETQDCLKDFF_SETASIC设计流程123456ABCD654321DCBAT itleN um berR evisionSizeCD ate:23-A pr-2001Sheet of File:C :tankem inPH ScktD SPD E C R E G .ddbD raw n B y:D SP_A 0U 8K _E R

6、R O R R D C SG E N _ST A T U SFL A G R D C SSL O T _SY N FL A G R D C SD spdecreg_R D C S8*8*U 8K _E R R O R _15_07:0U 8K _E R R O R _15_015:8U 8K _L O A D FL A G _7_0D SP_100m s_SE T 6 T est_m ode ,2b0D SP_D _D spdecregD SP_V SW R 1D SP_V SW R R D C S1D SP_V SW R 2D SP_V SW R 3D SP_V SW R 4D SP_V S

7、W R R D C S2D SP_V SW R R D C S3D SP_V SW R R D C S48*8*8*8*8*8*常数的补值ASIC设计流程3.2 3.2 代码实现代码实现 /-=ZTEIC CO.LTD.=-/ Information contained in this Confidential and Proprietary work has been obtained by ZTEIC CO / LTD。This Software may be used onlu as authorized by a licensing agreement from Limited/ CO

8、PYRIGHT (C) 2001 ZTEIC DESIGN Limited/ ALL RIGHTS RESERVED/ The entire notice above must be displayed on all authorized copies./ Copies may be made only to the extended consent by a licensing agreement/ from ZTEIC Limited./-/ Project and Control Information/- / Project Name : ZPCO1/ Last Version : 1

9、.0/ This Version : 1.1/ This module name : Adsample_rd_cs/ This file generated by : Tankemin-2000/12/16/ This file updated by : Tankemin-2001/03/09/-/ Included Contents in this Module/ File format : Verilog/ Include file name(s) :/ Include Module(s) Name :/ Function Block(s) Name :/ Task Block(s) Na

10、me ASIC设计流程/=timescale 1ns/1ns /-module Adsample_rd_cs ( /input from the clock chip outside CLK_19M2, /output to Adsample_ram_wraddr and the chip outside ADRDn AD_DATA_REG ); /Inputs input CLK_19M2; /the system main clock input SAMPLE_OUT;/the startup signal for AD sampling /Outputs output ADRDn;/th

11、e write clock of the ad ram output ADCSn;/the chip select signal for ad /- / Adsample_rd_cs/ =/-/ Overview/=ASIC设计流程/ when the signal SAMPLE_OUT appears,after two 3.84MHz clock periods,the signal/ ADCSn changes to be low,lasting two 3.84MHz clock periods,during the other / times it is high;and after

12、 three 3.84MHz clock periods,the signal ADRDn / changes to be low,lasting one 3.84MHz clock periods,during the other times it/ it is high/=/-/ Wire declarations/-/ (1) Module input signals/- wire CLK_19M2; /the system main clock wire Resetn;/the global reset signal / (2) Module internal signals/- wi

13、re 2:0 CNT_RD_CS_temp; /the tempary value of the CNT_RD_CS wire 2:0 CNT_RD_CS_ADD; /the adder of the CNT_RD_CS_ADD / (3) Module output signals/- wire ADRDn;/the write clock of the ad ram wire ADCSn;/the chip select signal for ad /-/ Register declarations/-/ Module internal signals/- reg ADRD;/the in

14、vertion of the signal ADRDn reg WRADDR_EN; /AD_WRADDR_5_0s enable signal for adding /-ASIC设计流程/ Main Verilog code/ =/-/the CNT_RD_CS generation/-/ every time when the signal SAMPLE_OUT appears,a counter start to add up by 1/ every 3.84MHz clock periods,the counter counter only one time.when the sing

15、al/ SAMPLE_OUT appears,the value of the counter is set to 4,every time the / CNT_3M84_eq4 is high,the counter add up by 1.after it counters up to 7,it / counters to zero and keep its value/- assign CNT_RD_CS_ADD_MLB = CNT_RD_CS2 & CNT_3M84_eq4; assign CNT_RD_CS_ADD = 2b0,CNT_RD_CS_ADD_MLB; assig

16、n CNT_RD_CS_temp = SAMPLE_OUT ? 3b100 : C N T _ R D _ C S + CNT_RD_CS_ADD; always (posedge CLK_19M2 or negedge Resetn) begin if (!Resetn) CNT_RD_CS = 3b0; else CNT_RD_CS = CNT_RD_CS_temp; end /-/-/the ADCSn generation/-/ CNT_RD_CS1 is the inversion of the ADCSn/-ASIC设计流程 always (posedge CLK_19M2 or

17、negedge Resetn) begin if ( !Resetn ) ADCS = 1b0; else ADCS = CNT_RD_CS1; end assign ADCSn = ADCS; /-/end of the module endmodule /-=END=-ASIC设计流程3.3 3.3 功能验证功能验证激励文件 通过仿真器，提取波形，检查电路的功能。ASIC设计流程3.4 3.4 电路综合电路综合 加工厂家提供宏单元 编写综合脚本文件，调入加工厂家的工艺库和宏单元，将电路语言映射到电路的网表文件 ASIC设计流程3.5 3.5 综合后的功能验证综合后的功能验证利用综合生成的网

18、表文件，进行电路仿真。 ASIC设计流程4. 4. 系统整合系统整合整合功能验证测试向量ASIC设计流程4.1 4.1 整合整合整合过程 综合脚本文件 Zpc01_core 的综合QpskclockDspdecregTop1AdsampleTop2BootdecTop3CpudecregTop4TimingTop5UintTop6TestTop7QpsksendTop8RecrfpllTop9QpskrcvZpc01_core整合整合1整合整合2整合整合3整合整合4整合整合5整合整合6整合整合7整合整合8整合整合9整合整合10Top1_tb功能验证功能验证1Top2_tb功能验证功能验证2Top3_tb功能验证功能验证3Top4_tb功能验证功能验证4Top5_tb功能验证功能验证5Top6_tb功能验证功能验证6Top7_tb功能验证功能