北邮数电实验VHDL源代码完整2013年

1、北邮数电实验VHDL源代码完整版注：北邮信通院数电实验，大二下共四次实验，以下为四次实验的完整代码，仅供参考，希望学弟学妹在抄代码的时候了解每一行代码的含义。知识是自己的。别忘了，北邮的未来靠你们。注意事项：1学校部分电脑打不开07版word文件（后缀docx），建议大家准备一份TXT以防万一2运行出错时可能是你输入有误，比如中文和英文符号弄错了3数电实验很简单，但要心细，一定要按老师说的做4数电实验报告千万不要抄袭，老师判断力很强实验一：半加器老师会给出，全加器是画图，怎么画书上有，不用源代码。实验二：（1）3位二进制数比较器LIBRARY IEEE;USE IEEE.STD_LOGIC_1

2、164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY comp3 IS PORT(A:IN STD_LOGIC_VECTOR(2 DOWNTO 0); B:IN STD_LOGIC_VECTOR(2 DOWNTO 0); YA,YB,YC:OUT STD_LOGIC);END comp3;ARCHITECTURE behave OF comp3 ISBEGIN PROCESS(A,B) BEGIN IF(A>B)THEN YA<='1'YB<='0'YC<='0' ELSIF(A&l

3、t;B)THEN YA<='0'YB<='1'YC<='0' ELSE YA<='0'YB<='0'YC<='1' END IF; END PROCESS;END behave;（2）4选1数据选择器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY mux4 IS PORT(A:IN STD_LOGIC_VECTOR(1 DOWNTO 0); D0,D1,

4、D2,D3:IN STD_LOGIC; Y,YB:OUT STD_LOGIC);END mux4;ARCHITECTURE behave OF mux4 IS BEGIN PROCESS(A,D0,D1,D2,D3) BEGIN CASE A IS WHEN"00"=> Y<=D0;YB <= NOT D0; WHEN"01"=> Y<=D1;YB <= NOT D1; WHEN"10"=> Y<=D2;YB <= NOT D2; WHEN"11"=> Y

5、<=D3;YB <= NOT D3; WHEN OTHERS=> Y<='Z'YB<='Z' END CASE; END PROCESS;END behave;（3）8421码转换为格雷码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY trans1 ISPORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END trans1;

6、ARCHITECTURE trans_gray OF trans1 ISBEGINB(0)<=A(0)XOR A(1);B(1)<=A(1)XOR A(2); B(2)<=A(2)XOR A(3);B(3)<=A(3);END trans_gray;（4）8421码转换为余三码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY sunyu_trans2 ISPORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:OUT STD_LOGI

7、C_VECTOR(3 DOWNTO 0);END sunyu_trans2;ARCHITECTURE trans_ex3 OF sunyu_trans2 ISBEGINPROCESS(A)BEGINCASE A ISWHEN"0000"=> B<="0011"WHEN"0001"=> B<="0100"WHEN"0010"=> B<="0101"WHEN"0011"=> B<="0110"

8、WHEN"0100"=> B<="0111"WHEN"0101"=> B<="1000"WHEN"0110"=> B<="1001"WHEN"0111"=> B<="1010"WHEN"1000"=> B<="1011"WHEN"1001"=> B<="1100"WHEN OTHERS=

9、> B<="ZZZZ"END CASE;END PROCESS;END trans_ex3;（5）数码管译码器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY sunyu_encoder ISPORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); C:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);END sunyu_encoder;ARCH

10、ITECTURE encoder_arch OF sunyu_encoder ISBEGINPROCESS(A)BEGINC<="011111"CASE A ISWHEN"0000"=> B<="1111110"-0WHEN"0001"=> B<="0110000"-1WHEN"0010"=> B<="1101101"-2WHEN"0011"=> B<="1111001&q

11、uot;-3WHEN"0100"=> B<="0110011"-4WHEN"0101"=> B<="1011011"-5WHEN"0110"=> B<="1011111"-6WHEN"0111"=> B<="1110000"-7WHEN"1000"=> B<="1111111"-8WHEN"1001"=> B&l

12、t;="1111011"-9WHEN OTHERS=> B<="ZZZZZZZ"END CASE;END PROCESS;END encoder_arch;实验三：注：以下的AAA（1）（2）（3）（4）为课前做好的，但课上老师要求有了些变化，实际上机的代码在下面BBB中AAA（1）带异步复位的四位二进制减计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count_1 ISPORT(clk,reset:IN STD_LOGIC

13、;q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END count_1;ARCHITECTURE a OF count_1 ISSIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(clk,reset)BEGINIF reset='0' THENq_temp <="1111"ELSIF clk'EVENT AND clk='1' THENq_temp <=q_temp-1;END IF;END PROCESS;q<= q_temp;EN

14、D a;（2）带异步复位的8421码十进制计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count_BCD ISPORT(clk,reset:IN STD_LOGIC;q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END count_BCD;ARCHITECTURE a OF count_BCD ISSIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(clk,reset)BEGINIF res

15、et='0' THENq_temp <="0000"ELSIF clk'EVENT AND clk='1' THENIF q_temp="1001" THENq_temp <="0000"ELSE q_temp <=q_temp+1;END IF;END IF;END PROCESS;q<= q_temp;END a;（3）分频器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL

16、;ENTITY div_12 ISPORT(clk:IN STD_LOGIC;clear:IN STD_LOGIC;clk_out:OUT STD_LOGIC);END div_12;ARCHITECTURE a OF div_12 ISSIGNAL temp:INTEGER RANGE 0 TO 11;BEGINp1:PROCESS(clear,clk)BEGINIF clear='0'THENtemp<=0;ELSIF clk'EVENT AND clk='1' THENIF temp=11 THENtemp<=0;ELSE temp&l

17、t;=temp+1;END IF;END IF;END PROCESS p1;p2:PROCESS(temp)BEGINIF temp<6 THENclk_out<='0'ELSE clk_out<='1'END IF;END PROCESS p2;END a;（4）带异步复位的四位环形计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ring ISPORT(clk,reset:IN STD_LOGIC;countout:OUT

18、STD_LOGIC_VECTOR(3 DOWNTO 0);END ring;ARCHITECTURE behave OF ring ISSIGNAL nextcount:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(clk,reset) -0001-0010-0100-1000-0001BEGINIF reset='0' THEN nextcount<="0001"ELSIF clk'EVENT AND clk='1' THENCASE nextcount ISWHEN"0001&

19、quot;=> nextcount<="0010"WHEN"0010"=> nextcount<="0100"WHEN"0100"=> nextcount<="1000"WHEN OTHERS=> nextcount<="0001"END CASE;END IF;END PROCESS;countout<=nextcount;END behave;BBBLIBRARY IEEE;USE IEEE.STD_LOGIC_116

20、4.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count_BCD ISPORT(clk,reset:IN STD_LOGIC;q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END count_BCD;ARCHITECTURE a OF count_BCD ISSIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(clk,reset)BEGINIF reset='1' THENq_temp <="0000"ELSIF clk

21、9;EVENT AND clk='1' THENIF q_temp="1001" THENq_temp <="0000"ELSE q_temp <=q_temp+1;END IF;END IF;END PROCESS;q<= q_temp;END a;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ring ISPORT(clk,reset:IN STD_LOGIC;-clk_out:out STD_LOGIC

22、;countout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ring;ARCHITECTURE behave OF ring ISSIGNAL nextcount:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL temp:STD_LOGIC;BEGINp1:PROCESS(clk)VARIABLE count:integer range 0 to 25000000;BEGINIF( clk'EVENT AND clk='1' )THENIF (count=25000000) THENcount:=0;temp&l

23、t;=not temp;ELSE count:=count+1;END IF;END IF;END PROCESS p1;-clk_out<=temp;p2:PROCESS(temp,reset) -0001-0010-0100-1000-0001BEGINIF reset='1' THEN nextcount<="0001"ELSIF temp'EVENT AND temp='1' THENCASE nextcount ISWHEN"0001"=> nextcount<="001

24、0"WHEN"0010"=> nextcount<="0100"WHEN"0100"=> nextcount<="1000"WHEN OTHERS=> nextcount<="0001"END CASE;END IF;END PROCESS p2;countout<=nextcount;END behave;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.

25、ALL;ENTITY div_12new ISPORT(clk:IN STD_LOGIC;clear:IN STD_LOGIC;clk_out:OUT STD_LOGIC);END div_12new;ARCHITECTURE a OF div_12new ISSIGNAL temp:STD_LOGIC;BEGINPROCESS(clear,clk)VARIABLE count:integer range 0 to 5;BEGINif (clear='1') thencount:=0;ELSIF( clk'EVENT AND clk='1' )THENI

26、F (count=5) THENcount:=0;temp<=not temp;ELSE count:=count+1;END IF;END IF;END PROCESS;clk_out<=temp;END a;实验四：这个稍有难度，而且书上没有多少参考代码，仔细研究哦（1）数码管显示012345library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity nixietube1 isport(clk: in std_logic;partout:out std_logic_vector(

27、6 downto 0);catout: out std_logic_vector(5 downto 0);end nixietube1;architecture a of nixietube1 issignal part: std_logic_vector(6 downto 0);signal cat: std_logic_vector(5 downto 0);signal tempclk: std_logic;signal count: integer range 0 to 50000;beginp1:process(clk)beginif(clk'event and clk=

28、9;1')thenif count=50000 thencount<=0;tempclk<= not tempclk;elsecount<=count+1;end if;end if;end process p1;p2:process(tempclk)beginif(tempclk'event and tempclk='1')thencase cat iswhen"111110"=> cat<="011111"part<="1111110" -0when"0

29、11111"=> cat<="101111"part<="0110000" -1when"101111"=> cat<="110111"part<="1101101" -2when"110111"=> cat<="111011"part<="1111001" -3when"111011"=> cat<="111101"pa

30、rt<="0110011" -4when"111101"=> cat<="111110"part<="1011011" -5when others => cat<="011111"part<="1111110" -0end case;end if;end process p2;catout<=cat;partout<=part;end a;（2）数码管滚动显示012345library ieee;use ieee.std_

31、logic_1164.all;use ieee.std_logic_unsigned.all;entity shiyan12new2 isport(clk: in std_logic;partout:out std_logic_vector(6 downto 0);catout: out std_logic_vector(5 downto 0);end shiyan12new2;architecture a of shiyan12new2 issignal part: std_logic_vector(6 downto 0);signal cat: std_logic_vector(5 dow

32、nto 0);signal number: std_logic_vector(5 downto 0);signal tempclk: std_logic;-a clk(div 1)signal move: std_logic;-a clk(div 2)beginp1:process(clk)-div 1 (cat 0-5)variable count:integer range 0 to 50000:=0;beginif(clk'event and clk='1')thenif(count=50000)thencount:=0;tempclk<= not temp

33、clk;elsecount:=count+1;end if;end if;end process p1;p2:process(tempclk) beginif tempclk'event and tempclk='1' thencase cat iswhen"011111"=>cat<="101111"when"101111"=>cat<="110111"when"110111"=>cat<="111011"when

34、"111011"=>cat<="111101"when"111101"=>cat<="111110"when others =>cat<="011111"end case;end if;end process p2;catout<=cat;p3:process(clk)-div 2 (one cat and change) about 1Hzvariable count:integer range 0 to 25000000:=0;beginif (cl

35、k'event and clk='1') thenif (count=25000000) thencount:=0;move<=not move;elsecount:=count+1;end if;end if;end process p3;p4:process(tempclk,move)-make numbersvariable judge1:integer range 0 to 1:=0;- 1 when "move" come variable judge2:integer range 0 to 1:=0;beginif (move

36、9;event and move='1') then judge1:=1;end if;if (tempclk'event and tempclk='1') thenif (judge1=0) then-when move donnot comecase number iswhen"011111"=>number<="101111"when"101111"=>number<="110111"when"110111"=>numb

37、er<="111011"when"111011"=>number<="111101"when"111101"=>number<="111110"when others =>number<="011111"end case;judge2:=0;elsecase number iswhen"011111"=>number<="110111"when"101111"=&

38、gt;number<="111011"when"110111"=>number<="111101"when"111011"=>number<="111110"when"111110"=>number<="101111"when others =>number<="011111"end case;judge2:=1;end if;end if;if judge2=1 thenjudge

39、1:=0;end if;end process p4;p5:process(number)begincase number iswhen"011111"=>part<="1111110"when"101111"=>part<="0110000"when"110111"=>part<="1101101"when"111011"=>part<="1111001"when"111101

40、"=>part<="0110011"when"111110"=>part<="1011011"when others =>part<="1111110"end case;end process p5;partout<=part;end a;（3）数码管滚动显示012345，且用全灭的数码管填充右边，直至全灭library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity

41、shiyan12new3 isport(clk: in std_logic;partout:out std_logic_vector(6 downto 0);catout: out std_logic_vector(5 downto 0);end shiyan12new3;architecture a of shiyan12new3 issignal part: std_logic_vector(6 downto 0);signal cat: std_logic_vector(5 downto 0);signal number: std_logic_vector(5 downto 0);sig

42、nal tempclk: std_logic;-a clk(div 1)signal move: std_logic;-a clk(div 2)beginp1:process(clk)-div 1 (cat 0-5)variable count:integer range 0 to 50000 :=0;beginif(clk'event and clk='1')thenif(count=50000)thencount:=0;tempclk<= not tempclk;elsecount:=count+1;end if;end if;end process p1;p

43、2:process(tempclk)variable count: integer range 0 to 11;variable temp:std_logic_vector(5 downto 0);beginif (move'event and move='1')thenif count=11 thencount:=0;else count:=count+1;end if;end if;if tempclk'event and tempclk='1' thencase temp iswhen"011111"=>temp:

44、="101111"when"101111"=>temp:="110111"when"110111"=>temp:="111011"when"111011"=>temp:="111101"when"111101"=>temp:="111110"when others =>temp:="011111"end case;end if;case count iswhen 0

45、=>cat<=(temp or "000000");-cat is active lowwhen 1 =>cat<=(temp or "000001");when 2 =>cat<=(temp or "000011");when 3 =>cat<=(temp or "000111");when 4 =>cat<=(temp or "001111");when 5 =>cat<=(temp or "011111&qu

46、ot;);when 6 =>cat<=(temp or "111111");when 7 =>cat<=(temp or "111110");when 8 =>cat<=(temp or "111100");when 9 =>cat<=(temp or "111000");when 10=>cat<=(temp or "110000");when 11=>cat<=(temp or "100000");end case;catout<=cat;end process p2;p3:process(clk) -div 2 (one cat and change)about 1Hzvariable count:integer range 0 to 25000000:=0;beginif (clk'event and clk='1') thenif (count=25000000) thencount:=0;move<=not move;elsecount:=count+1;end if;end if;en